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arm64: dts: qcom: clear the warnings caused by empty dma-ranges
The scripts/dtc/checks.c requires that the node have empty "dma-ranges" property must have the same "#address-cells" and "#size-cells" values as the parent node. Otherwise, the following warnings is reported: arch/arm64/boot/dts/qcom/ipq6018.dtsi:185.3-14: Warning \ (dma_ranges_format): /soc:dma-ranges: empty "dma-ranges" property but \ its #address-cells (1) differs from / (2) arch/arm64/boot/dts/qcom/ipq6018.dtsi:185.3-14: Warning \ (dma_ranges_format): /soc:dma-ranges: empty "dma-ranges" property but \ its #size-cells (1) differs from / (2) Arnd Bergmann figured out why it's necessary: Also note that the #address-cells=<1> means that any device under this bus is assumed to only support 32-bit addressing, and DMA will have to go through a slow swiotlb in the absence of an IOMMU. Suggested-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Link: https://lore.kernel.org/r/20201016090833.1892-3-thunder.leizhen@huawei.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Zhen Lei
Bjorn Andersson
parent
ef9a5d188d
commit
77e9c198b1
@ -179,22 +179,22 @@
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};
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0 0 0 0 0x0 0xffffffff>;
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dma-ranges;
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compatible = "simple-bus";
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prng: qrng@e1000 {
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compatible = "qcom,prng-ee";
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reg = <0xe3000 0x1000>;
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reg = <0x0 0xe3000 0x0 0x1000>;
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clocks = <&gcc GCC_PRNG_AHB_CLK>;
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clock-names = "core";
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};
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cryptobam: dma@704000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x00704000 0x20000>;
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reg = <0x0 0x00704000 0x0 0x20000>;
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interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
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clock-names = "bam_clk";
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@ -206,7 +206,7 @@
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crypto: crypto@73a000 {
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compatible = "qcom,crypto-v5.1";
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reg = <0x0073a000 0x6000>;
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reg = <0x0 0x0073a000 0x0 0x6000>;
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clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
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<&gcc GCC_CRYPTO_AXI_CLK>,
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<&gcc GCC_CRYPTO_CLK>;
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@ -217,7 +217,7 @@
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tlmm: pinctrl@1000000 {
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compatible = "qcom,ipq6018-pinctrl";
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reg = <0x01000000 0x300000>;
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reg = <0x0 0x01000000 0x0 0x300000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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@ -235,7 +235,7 @@
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gcc: gcc@1800000 {
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compatible = "qcom,gcc-ipq6018";
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reg = <0x01800000 0x80000>;
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reg = <0x0 0x01800000 0x0 0x80000>;
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clocks = <&xo>, <&sleep_clk>;
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clock-names = "xo", "sleep_clk";
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#clock-cells = <1>;
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@ -244,17 +244,17 @@
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tcsr_mutex_regs: syscon@1905000 {
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compatible = "syscon";
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reg = <0x01905000 0x8000>;
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reg = <0x0 0x01905000 0x0 0x8000>;
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};
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tcsr_q6: syscon@1945000 {
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compatible = "syscon";
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reg = <0x01945000 0xe000>;
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reg = <0x0 0x01945000 0x0 0xe000>;
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};
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blsp_dma: dma@7884000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x07884000 0x2b000>;
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reg = <0x0 0x07884000 0x0 0x2b000>;
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interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "bam_clk";
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@ -264,7 +264,7 @@
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blsp1_uart3: serial@78b1000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x078b1000 0x200>;
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reg = <0x0 0x078b1000 0x0 0x200>;
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interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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@ -276,7 +276,7 @@
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compatible = "qcom,spi-qup-v2.2.1";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x078b5000 0x600>;
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reg = <0x0 0x078b5000 0x0 0x600>;
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
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@ -291,7 +291,7 @@
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compatible = "qcom,spi-qup-v2.2.1";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x078b6000 0x600>;
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reg = <0x0 0x078b6000 0x0 0x600>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
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@ -306,7 +306,7 @@
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compatible = "qcom,i2c-qup-v2.2.1";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x078b6000 0x600>;
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reg = <0x0 0x078b6000 0x0 0x600>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
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@ -321,7 +321,7 @@
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compatible = "qcom,i2c-qup-v2.2.1";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x078b7000 0x600>;
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reg = <0x0 0x078b7000 0x0 0x600>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
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@ -336,24 +336,24 @@
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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#interrupt-cells = <0x3>;
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reg = <0x0b000000 0x1000>, /*GICD*/
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<0x0b002000 0x1000>, /*GICC*/
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<0x0b001000 0x1000>, /*GICH*/
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<0x0b004000 0x1000>; /*GICV*/
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reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/
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<0x0 0x0b002000 0x0 0x1000>, /*GICC*/
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<0x0 0x0b001000 0x0 0x1000>, /*GICH*/
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<0x0 0x0b004000 0x0 0x1000>; /*GICV*/
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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watchdog@b017000 {
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compatible = "qcom,kpss-wdt";
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interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
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reg = <0x0b017000 0x40>;
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reg = <0x0 0x0b017000 0x0 0x40>;
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clocks = <&sleep_clk>;
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timeout-sec = <10>;
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};
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apcs_glb: mailbox@b111000 {
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compatible = "qcom,ipq6018-apcs-apps-global";
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reg = <0x0b111000 0x1000>;
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reg = <0x0 0x0b111000 0x0 0x1000>;
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#clock-cells = <1>;
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clocks = <&a53pll>, <&xo>;
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clock-names = "pll", "xo";
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@ -362,7 +362,7 @@
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a53pll: clock@b116000 {
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compatible = "qcom,ipq6018-a53pll";
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reg = <0x0b116000 0x40>;
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reg = <0x0 0x0b116000 0x0 0x40>;
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#clock-cells = <0>;
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clocks = <&xo>;
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clock-names = "xo";
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@ -377,68 +377,68 @@
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};
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timer@b120000 {
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#address-cells = <1>;
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#size-cells = <1>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0x0b120000 0x1000>;
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reg = <0x0 0x0b120000 0x0 0x1000>;
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clock-frequency = <19200000>;
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frame@b120000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0b121000 0x1000>,
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<0x0b122000 0x1000>;
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reg = <0x0 0x0b121000 0x0 0x1000>,
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<0x0 0x0b122000 0x0 0x1000>;
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};
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frame@b123000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xb123000 0x1000>;
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reg = <0x0 0xb123000 0x0 0x1000>;
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status = "disabled";
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};
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frame@b124000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0b124000 0x1000>;
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reg = <0x0 0x0b124000 0x0 0x1000>;
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status = "disabled";
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};
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frame@b125000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0b125000 0x1000>;
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reg = <0x0 0x0b125000 0x0 0x1000>;
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status = "disabled";
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};
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frame@b126000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0b126000 0x1000>;
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reg = <0x0 0x0b126000 0x0 0x1000>;
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status = "disabled";
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};
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frame@b127000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0b127000 0x1000>;
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reg = <0x0 0x0b127000 0x0 0x1000>;
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status = "disabled";
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};
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frame@b128000 {
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frame-number = <6>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0b128000 0x1000>;
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reg = <0x0 0x0b128000 0x0 0x1000>;
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status = "disabled";
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};
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};
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q6v5_wcss: remoteproc@cd00000 {
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compatible = "qcom,ipq8074-wcss-pil";
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reg = <0x0cd00000 0x4040>,
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<0x004ab000 0x20>;
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reg = <0x0 0x0cd00000 0x0 0x4040>,
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<0x0 0x004ab000 0x0 0x20>;
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reg-names = "qdsp6",
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"rmb";
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interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>,
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