dt-bindings: devfreq: rk3399_dmc: Specify idle params in nanoseconds

It's inefficient to use the same number of cycles for all OPPs, since
lower frequencies make for longer idle times. Let's specify the idle
time instead, so software can pick the optimal number of cycles on its
own.

NB: these bindings aren't used anywhere yet.

Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
This commit is contained in:
Brian Norris 2022-03-08 11:08:50 -08:00 committed by Chanwoo Choi
parent 4de8fd02a5
commit 77c188085b

View File

@ -54,42 +54,52 @@ properties:
being used.
rockchip,pd_idle:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
Configure the PD_IDLE value. Defines the power-down idle period in which
memories are placed into power-down mode if bus is idle for PD_IDLE DFI
clock cycles.
See also rockchip,pd-idle-ns.
rockchip,sr_idle:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
Configure the SR_IDLE value. Defines the self-refresh idle period in
which memories are placed into self-refresh mode if bus is idle for
SR_IDLE * 1024 DFI clock cycles (DFI clocks freq is half of DRAM clock).
See also rockchip,sr-idle-ns.
default: 0
rockchip,sr_mc_gate_idle:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
Defines the memory self-refresh and controller clock gating idle period.
Memories are placed into self-refresh mode and memory controller clock
arg gating started if bus is idle for sr_mc_gate_idle*1024 DFI clock
cycles.
See also rockchip,sr-mc-gate-idle-ns.
rockchip,srpd_lite_idle:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
Defines the self-refresh power down idle period in which memories are
placed into self-refresh power down mode if bus is idle for
srpd_lite_idle * 1024 DFI clock cycles. This parameter is for LPDDR4
only.
See also rockchip,srpd-lite-idle-ns.
rockchip,standby_idle:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
Defines the standby idle period in which memories are placed into
self-refresh mode. The controller, pi, PHY and DRAM clock will be gated
if bus is idle for standby_idle * DFI clock cycles.
See also rockchip,standby-idle-ns.
rockchip,dram_dll_dis_freq:
deprecated: true
@ -272,6 +282,37 @@ properties:
strength.
default: 60
rockchip,pd-idle-ns:
description:
Configure the PD_IDLE value in nanoseconds. Defines the power-down idle
period in which memories are placed into power-down mode if bus is idle
for PD_IDLE nanoseconds.
rockchip,sr-idle-ns:
description:
Configure the SR_IDLE value in nanoseconds. Defines the self-refresh idle
period in which memories are placed into self-refresh mode if bus is idle
for SR_IDLE nanoseconds.
default: 0
rockchip,sr-mc-gate-idle-ns:
description:
Defines the memory self-refresh and controller clock gating idle period in nanoseconds.
Memories are placed into self-refresh mode and memory controller clock
arg gating started if bus is idle for sr_mc_gate_idle nanoseconds.
rockchip,srpd-lite-idle-ns:
description:
Defines the self-refresh power down idle period in which memories are
placed into self-refresh power down mode if bus is idle for
srpd_lite_idle nanoseonds. This parameter is for LPDDR4 only.
rockchip,standby-idle-ns:
description:
Defines the standby idle period in which memories are placed into
self-refresh mode. The controller, pi, PHY and DRAM clock will be gated
if bus is idle for standby_idle nanoseconds.
required:
- compatible
- devfreq-events
@ -295,11 +336,11 @@ examples:
clock-names = "dmc_clk";
operating-points-v2 = <&dmc_opp_table>;
center-supply = <&ppvar_centerlogic>;
rockchip,pd_idle = <0x40>;
rockchip,sr_idle = <0x2>;
rockchip,sr_mc_gate_idle = <0x3>;
rockchip,srpd_lite_idle = <0x4>;
rockchip,standby_idle = <0x2000>;
rockchip,pd-idle-ns = <160>;
rockchip,sr-idle-ns = <10240>;
rockchip,sr-mc-gate-idle-ns = <40960>;
rockchip,srpd-lite-idle-ns = <61440>;
rockchip,standby-idle-ns = <81920>;
rockchip,ddr3_odt_dis_freq = <333000000>;
rockchip,lpddr3_odt_dis_freq = <333000000>;
rockchip,lpddr4_odt_dis_freq = <333000000>;