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MIPS: Clarify mips_cm_is64 documentation

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The documentation for mips_cm_is64 implied that the width of the CM GCRs
would change depending upon the CPU, which is not true. Reword the
explanation to be clearer that the GCR width is purely dependent upon
the version of the CM.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/11185/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Paul Burton 2015-09-22 10:26:37 -07:00 committed by Ralf Baechle
parent 6759657341
commit 7784494ae7
1 changed files with 6 additions and 6 deletions
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12
arch/mips/include/asm/mips-cm.h
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@ -36,12 +36,12 @@ extern phys_addr_t __mips_cm_phys_base(void);
/* /*
* mips_cm_is64 - determine CM register width * mips_cm_is64 - determine CM register width
* *
* The CM register width is processor and CM specific. A 64-bit processor * The CM register width is determined by the version of the CM, with CM3
* usually has a 64-bit CM and a 32-bit one has a 32-bit CM but a 64-bit * introducing 64 bit GCRs and all prior CM versions having 32 bit GCRs.
* processor could come with a 32-bit CM. Moreover, accesses on 64-bit CMs * However we may run a kernel built for MIPS32 on a system with 64 bit GCRs,
* can be done either using regular 64-bit load/store instructions, or 32-bit * or vice-versa. This variable indicates the width of the memory accesses
* load/store instruction on 32-bit register pairs. We opt for using 64-bit * that the kernel will perform to GCRs, which may differ from the actual
* accesses on 64-bit CMs and kernels and 32-bit in any other case. * width of the GCRs.
* *
* It's set to 0 for 32-bit accesses and 1 for 64-bit accesses. * It's set to 0 for 32-bit accesses and 1 for 64-bit accesses.
*/ */