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drm/i915/skl: Implement WaEnableLbsSlaRetryTimerDecrement
This W/A is put in a gen9 specific function because it may well be needed on other gen9 platforms. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Nick Hoath <nicholas.hoath@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -5285,6 +5285,9 @@ enum skl_disp_power_wells {
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#define HSW_SCRATCH1 0xb038
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#define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27)
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#define BDW_SCRATCH1 0xb11c
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#define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1<<2)
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/* PCH */
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/* south display engine interrupt: IBX */
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@ -52,10 +52,21 @@
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#define INTEL_RC6p_ENABLE (1<<1)
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#define INTEL_RC6pp_ENABLE (1<<2)
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static void gen9_init_clock_gating(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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/* WaEnableLbsSlaRetryTimerDecrement:skl */
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I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
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GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
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}
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static void skl_init_clock_gating(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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gen9_init_clock_gating(dev);
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if (INTEL_REVID(dev) == SKL_REVID_A0) {
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/*
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* WaDisableSDEUnitClockGating:skl
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