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This allows that device tree enables platform to setup a runtime IO mapping for the chip id
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJReVkKAAoJEA0Cl+kVi2xqQMQP/3r2I9lir6uKXF/WIFgzYMUp 6PHaISZex6gvBOUmVKo2akkH8iqQNNqQLjt0TQ/ZMQ3HByj0A6qZ+RnMZhReNs1d 6tu/PaE5pV5cp4I97fx0MyHoLsySqmC9fbwM78YDCb4hwpcDLpvK45CMvQ4Uc56N xvIC0DGhLK5kZrBy3+SolfHvOMn3F5Lfc6+VpZxxZgTUS1oMTtTwe/iUOjnhEL5C Qnjkpc2R4IERMRNtNgeWOwjMwj+vHv2tIz0K+3/hXe34AqYX0gFYm2mB88Bi5tK8 lUt7e1hz9QKobPgike7rCtj/Ap8EkFuC0yGLOiLHA21HeyiTLCkV77ennSs/00kc ijeQmG382C8CqDvjKpXhaP7gPQQcUIC95EncS1ts+iM/dcbUjbYdiV677QjARm+U BMIw/fzTIs3uI2TRA7RMzQtlsbTfdVtVZJJx2HfpiKdpQWhT+B+mCS/KOf22D9cj KGoF7AKvLAUIlbYdgB2eloavM3tAYTJtuWQEnmp//YtcOUVaESDRn/01Y7lDYpLX VF8jayav4pu2cDiSnvFDsBj7gGlFhdcu4pPwpoRvKVKeKJZJHwo/0Yv0f3dNbqKa 2loO9AdgSH//g5Y3SPbVBr4HYCSpn+S0K63hmwXhpxbHtQsj2D1OQ640YSggdkj1 tU4rwoM24digFbOZvrQk =sRUG -----END PGP SIGNATURE----- Merge tag 'late-exynos-v3-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into late/dt From Kukjin Kim: This allows that device tree enables platform to setup a runtime IO mapping for the chip id * tag 'late-exynos-v3-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: dts: Add chip-id controller node on Exynos4/5 SoC ARM: EXYNOS: Create virtual I/O mapping for Chip-ID controller using device tree Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
commit
775c4f66fd
@ -38,6 +38,11 @@
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i2c7 = &i2c_7;
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i2c7 = &i2c_7;
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};
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};
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chipid@10000000 {
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compatible = "samsung,exynos4210-chipid";
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reg = <0x10000000 0x100>;
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};
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pd_mfc: mfc-power-domain@10023C40 {
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pd_mfc: mfc-power-domain@10023C40 {
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compatible = "samsung,exynos4210-pd";
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compatible = "samsung,exynos4210-pd";
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reg = <0x10023C40 0x20>;
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reg = <0x10023C40 0x20>;
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@ -51,6 +51,11 @@
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pinctrl3 = &pinctrl_3;
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pinctrl3 = &pinctrl_3;
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};
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};
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chipid@10000000 {
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compatible = "samsung,exynos4210-chipid";
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reg = <0x10000000 0x100>;
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};
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pd_gsc: gsc-power-domain@0x10044000 {
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pd_gsc: gsc-power-domain@0x10044000 {
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compatible = "samsung,exynos4210-pd";
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compatible = "samsung,exynos4210-pd";
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reg = <0x10044000 0x20>;
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reg = <0x10044000 0x20>;
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@ -119,17 +119,6 @@ static struct map_desc exynos_iodesc[] __initdata = {
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},
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},
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};
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};
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#ifdef CONFIG_ARCH_EXYNOS5
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static struct map_desc exynos5440_iodesc[] __initdata = {
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{
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.virtual = (unsigned long)S5P_VA_CHIPID,
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.pfn = __phys_to_pfn(EXYNOS5440_PA_CHIPID),
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.length = SZ_4K,
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.type = MT_DEVICE,
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},
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};
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#endif
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static struct map_desc exynos4_iodesc[] __initdata = {
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static struct map_desc exynos4_iodesc[] __initdata = {
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{
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{
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.virtual = (unsigned long)S3C_VA_SYS,
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.virtual = (unsigned long)S3C_VA_SYS,
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@ -320,6 +309,31 @@ void __init exynos_init_late(void)
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exynos_pm_late_initcall();
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exynos_pm_late_initcall();
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}
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}
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#ifdef CONFIG_OF
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int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
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int depth, void *data)
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{
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struct map_desc iodesc;
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__be32 *reg;
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unsigned long len;
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if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") &&
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!of_flat_dt_is_compatible(node, "samsung,exynos5440-clock"))
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return 0;
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reg = of_get_flat_dt_prop(node, "reg", &len);
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if (reg == NULL || len != (sizeof(unsigned long) * 2))
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return 0;
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iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
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iodesc.length = be32_to_cpu(reg[1]) - 1;
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iodesc.virtual = (unsigned long)S5P_VA_CHIPID;
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iodesc.type = MT_DEVICE;
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iotable_init(&iodesc, 1);
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return 1;
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}
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#endif
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/*
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/*
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* exynos_map_io
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* exynos_map_io
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*
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*
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@ -328,19 +342,12 @@ void __init exynos_init_late(void)
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void __init exynos_init_io(struct map_desc *mach_desc, int size)
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void __init exynos_init_io(struct map_desc *mach_desc, int size)
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{
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{
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struct map_desc *iodesc = exynos_iodesc;
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#ifdef CONFIG_OF
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int iodesc_sz = ARRAY_SIZE(exynos_iodesc);
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if (initial_boot_params)
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#if defined(CONFIG_OF) && defined(CONFIG_ARCH_EXYNOS5)
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of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
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unsigned long root = of_get_flat_dt_root();
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else
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/* initialize the io descriptors we need for initialization */
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if (of_flat_dt_is_compatible(root, "samsung,exynos5440")) {
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iodesc = exynos5440_iodesc;
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iodesc_sz = ARRAY_SIZE(exynos5440_iodesc);
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}
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#endif
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#endif
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iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
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iotable_init(iodesc, iodesc_sz);
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if (mach_desc)
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if (mach_desc)
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iotable_init(mach_desc, size);
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iotable_init(mach_desc, size);
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@ -53,7 +53,6 @@
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#define EXYNOS4_PA_ONENAND_DMA 0x0C600000
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#define EXYNOS4_PA_ONENAND_DMA 0x0C600000
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#define EXYNOS_PA_CHIPID 0x10000000
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#define EXYNOS_PA_CHIPID 0x10000000
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#define EXYNOS5440_PA_CHIPID 0x00160000
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#define EXYNOS4_PA_SYSCON 0x10010000
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#define EXYNOS4_PA_SYSCON 0x10010000
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#define EXYNOS5_PA_SYSCON 0x10050100
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#define EXYNOS5_PA_SYSCON 0x10050100
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