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xtensa: fix TLB multihit exceptions
- set _PAGE_USER in the pte_clear to avoid having TLB multihit exceptions (see following threads for more details); http://lists.linux-xtensa.org/pipermail/linux-xtensa/Week-of-Mon-20130401/ http://lists.linux-xtensa.org/pipermail/linux-xtensa/Week-of-Mon-20130408/ - improved documentation of the PTE layout - fix PTE mapping for present and 'prot_none' pages for T1050 hw and earlier - fix pte_file offset and size - add check for the correct number of bits for swap type CC: piet.delaney@gmail.com CC: jcmvbkbc@gmail.com Signed-off-by: Chris Zankel <chris@zankel.net>
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Chris Zankel
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@ -5,7 +5,7 @@
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Copyright (C) 2001 - 2007 Tensilica Inc.
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* Copyright (C) 2001 - 2013 Tensilica Inc.
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*/
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#ifndef _XTENSA_PGTABLE_H
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@ -64,41 +64,82 @@
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* Virtual memory area. We keep a distance to other memory regions to be
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* on the safe side. We also use this area for cache aliasing.
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*/
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#define VMALLOC_START 0xC0000000
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#define VMALLOC_END 0xC7FEFFFF
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#define TLBTEMP_BASE_1 0xC7FF0000
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#define TLBTEMP_BASE_2 0xC7FF8000
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/*
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* Xtensa Linux config PTE layout (when present):
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* 31-12: PPN
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* 11-6: Software
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* 5-4: RING
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* 3-0: CA
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* For the Xtensa architecture, the PTE layout is as follows:
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*
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* Similar to the Alpha and MIPS ports, we need to keep track of the ref
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* and mod bits in software. We have a software "you can read
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* from this page" bit, and a hardware one which actually lets the
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* process read from the page. On the same token we have a software
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* writable bit and the real hardware one which actually lets the
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* process write to the page.
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* 31------12 11 10-9 8-6 5-4 3-2 1-0
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* +-----------------------------------------+
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* | | Software | HARDWARE |
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* | PPN | ADW | RI |Attribute|
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* +-----------------------------------------+
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* pte_none | MBZ | 01 | 11 | 00 |
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* +-----------------------------------------+
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* present | PPN | 0 | 00 | ADW | RI | CA | wx |
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* +- - - - - - - - - - - - - - - - - - - - -+
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* (PAGE_NONE)| PPN | 0 | 00 | ADW | 01 | 11 | 11 |
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* +-----------------------------------------+
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* swap | index | type | 01 | 11 | 00 |
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* +- - - - - - - - - - - - - - - - - - - - -+
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* file | file offset | 01 | 11 | 10 |
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* +-----------------------------------------+
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*
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* See further below for PTE layout for swapped-out pages.
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* For T1050 hardware and earlier the layout differs for present and (PAGE_NONE)
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* +-----------------------------------------+
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* present | PPN | 0 | 00 | ADW | RI | CA | w1 |
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* +-----------------------------------------+
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* (PAGE_NONE)| PPN | 0 | 00 | ADW | 01 | 01 | 00 |
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* +-----------------------------------------+
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*
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* Legend:
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* PPN Physical Page Number
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* ADW software: accessed (young) / dirty / writable
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* RI ring (0=privileged, 1=user, 2 and 3 are unused)
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* CA cache attribute: 00 bypass, 01 writeback, 10 writethrough
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* (11 is invalid and used to mark pages that are not present)
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* w page is writable (hw)
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* x page is executable (hw)
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* index swap offset / PAGE_SIZE (bit 11-31: 21 bits -> 8 GB)
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* (note that the index is always non-zero)
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* type swap type (5 bits -> 32 types)
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* file offset 26-bit offset into the file, in increments of PAGE_SIZE
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*
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* Notes:
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* - (PROT_NONE) is a special case of 'present' but causes an exception for
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* any access (read, write, and execute).
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* - 'multihit-exception' has the highest priority of all MMU exceptions,
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* so the ring must be set to 'RING_USER' even for 'non-present' pages.
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* - on older hardware, the exectuable flag was not supported and
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* used as a 'valid' flag, so it needs to be always set.
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* - we need to keep track of certain flags in software (dirty and young)
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* to do this, we use write exceptions and have a separate software w-flag.
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* - attribute value 1101 (and 1111 on T1050 and earlier) is reserved
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*/
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#define _PAGE_ATTRIB_MASK 0xf
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#define _PAGE_HW_EXEC (1<<0) /* hardware: page is executable */
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#define _PAGE_HW_WRITE (1<<1) /* hardware: page is writable */
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#define _PAGE_FILE (1<<1) /* non-linear mapping, if !present */
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#define _PAGE_PROTNONE (3<<0) /* special case for VM_PROT_NONE */
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/* None of these cache modes include MP coherency: */
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#define _PAGE_CA_BYPASS (0<<2) /* bypass, non-speculative */
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#define _PAGE_CA_WB (1<<2) /* write-back */
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#define _PAGE_CA_WT (2<<2) /* write-through */
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#define _PAGE_CA_MASK (3<<2)
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#define _PAGE_INVALID (3<<2)
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#define _PAGE_CA_INVALID (3<<2)
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/* We use invalid attribute values to distinguish special pte entries */
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#if XCHAL_HW_VERSION_MAJOR < 2000
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#define _PAGE_HW_VALID 0x01 /* older HW needed this bit set */
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#define _PAGE_NONE 0x04
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#else
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#define _PAGE_HW_VALID 0x00
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#define _PAGE_NONE 0x0f
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#endif
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#define _PAGE_FILE (1<<1) /* file mapped page, only if !present */
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#define _PAGE_USER (1<<4) /* user access (ring=1) */
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@ -108,19 +149,12 @@
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#define _PAGE_DIRTY (1<<7) /* software: page dirty */
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#define _PAGE_ACCESSED (1<<8) /* software: page accessed (read) */
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/* On older HW revisions, we always have to set bit 0 */
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#if XCHAL_HW_VERSION_MAJOR < 2000
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# define _PAGE_VALID (1<<0)
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#else
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# define _PAGE_VALID 0
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#endif
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#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
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#define _PAGE_PRESENT (_PAGE_VALID | _PAGE_CA_WB | _PAGE_ACCESSED)
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#ifdef CONFIG_MMU
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#define PAGE_NONE __pgprot(_PAGE_INVALID | _PAGE_USER | _PAGE_PROTNONE)
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#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
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#define _PAGE_PRESENT (_PAGE_HW_VALID | _PAGE_CA_WB | _PAGE_ACCESSED)
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#define PAGE_NONE __pgprot(_PAGE_NONE | _PAGE_USER)
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#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_USER)
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#define PAGE_COPY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_HW_EXEC)
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#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER)
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@ -132,9 +166,9 @@
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#define PAGE_KERNEL_EXEC __pgprot(_PAGE_PRESENT|_PAGE_HW_WRITE|_PAGE_HW_EXEC)
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#if (DCACHE_WAY_SIZE > PAGE_SIZE)
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# define _PAGE_DIRECTORY (_PAGE_VALID | _PAGE_ACCESSED)
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# define _PAGE_DIRECTORY (_PAGE_HW_VALID | _PAGE_ACCESSED | _PAGE_CA_BYPASS)
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#else
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# define _PAGE_DIRECTORY (_PAGE_VALID | _PAGE_ACCESSED | _PAGE_CA_WB)
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# define _PAGE_DIRECTORY (_PAGE_HW_VALID | _PAGE_ACCESSED | _PAGE_CA_WB)
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#endif
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#else /* no mmu */
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@ -202,12 +236,16 @@ static inline void pgtable_cache_init(void) { }
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/*
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* pte status.
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*/
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#define pte_none(pte) (pte_val(pte) == _PAGE_INVALID)
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#define pte_present(pte) \
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(((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_INVALID) \
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|| ((pte_val(pte) & _PAGE_PROTNONE) == _PAGE_PROTNONE))
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# define pte_none(pte) (pte_val(pte) == (_PAGE_CA_INVALID | _PAGE_USER))
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#if XCHAL_HW_VERSION_MAJOR < 2000
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# define pte_present(pte) ((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_CA_INVALID)
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#else
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# define pte_present(pte) \
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(((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_CA_INVALID) \
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|| ((pte_val(pte) & _PAGE_ATTRIB_MASK) == _PAGE_NONE))
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#endif
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#define pte_clear(mm,addr,ptep) \
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do { update_pte(ptep, __pte(_PAGE_INVALID)); } while(0)
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do { update_pte(ptep, __pte(_PAGE_CA_INVALID | _PAGE_USER)); } while (0)
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#define pmd_none(pmd) (!pmd_val(pmd))
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#define pmd_present(pmd) (pmd_val(pmd) & PAGE_MASK)
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@ -328,35 +366,23 @@ ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
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/*
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* Encode and decode a swap entry.
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*
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* Format of swap pte:
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* bit 0 MBZ
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* bit 1 page-file (must be zero)
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* bits 2 - 3 page hw access mode (must be 11: _PAGE_INVALID)
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* bits 4 - 5 ring protection (must be 01: _PAGE_USER)
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* bits 6 - 10 swap type (5 bits -> 32 types)
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* bits 11 - 31 swap offset / PAGE_SIZE (21 bits -> 8GB)
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* Format of file pte:
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* bit 0 MBZ
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* bit 1 page-file (must be one: _PAGE_FILE)
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* bits 2 - 3 page hw access mode (must be 11: _PAGE_INVALID)
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* bits 4 - 5 ring protection (must be 01: _PAGE_USER)
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* bits 6 - 31 file offset / PAGE_SIZE
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* Encode and decode a swap and file entry.
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*/
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#define SWP_TYPE_BITS 5
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#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS)
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#define __swp_type(entry) (((entry).val >> 6) & 0x1f)
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#define __swp_offset(entry) ((entry).val >> 11)
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#define __swp_entry(type,offs) \
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((swp_entry_t) {((type) << 6) | ((offs) << 11) | _PAGE_INVALID})
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((swp_entry_t){((type) << 6) | ((offs) << 11) | \
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_PAGE_CA_INVALID | _PAGE_USER})
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
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#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
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#define PTE_FILE_MAX_BITS 28
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#define pte_to_pgoff(pte) (pte_val(pte) >> 4)
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#define PTE_FILE_MAX_BITS 26
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#define pte_to_pgoff(pte) (pte_val(pte) >> 6)
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#define pgoff_to_pte(off) \
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((pte_t) { ((off) << 4) | _PAGE_INVALID | _PAGE_FILE })
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((pte_t) { ((off) << 6) | _PAGE_CA_INVALID | _PAGE_FILE | _PAGE_USER })
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#endif /* !defined (__ASSEMBLY__) */
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