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mm/hmm: documentation editorial update to HMM documentation
Update the documentation for HMM to fix minor typos and phrasing to be a bit more readable. Link: http://lkml.kernel.org/r/20180323005527.758-2-jglisse@redhat.com Signed-off-by: Ralph Campbell <rcampbell@nvidia.com> Signed-off-by: Jérôme Glisse <jglisse@redhat.com> Cc: Stephen Bates <sbates@raithlin.com> Cc: Jason Gunthorpe <jgg@mellanox.com> Cc: Logan Gunthorpe <logang@deltatee.com> Cc: Evgeny Baskakov <ebaskakov@nvidia.com> Cc: Mark Hairgrove <mhairgrove@nvidia.com> Cc: John Hubbard <jhubbard@nvidia.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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Ralph Campbell
Linus Torvalds
parent
d51d1e6450
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76ea470ce4
@ -1,151 +1,159 @@
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Heterogeneous Memory Management (HMM)
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Transparently allow any component of a program to use any memory region of said
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program with a device without using device specific memory allocator. This is
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becoming a requirement to simplify the use of advance heterogeneous computing
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where GPU, DSP or FPGA are use to perform various computations.
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Provide infrastructure and helpers to integrate non conventional memory (device
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memory like GPU on board memory) into regular kernel code path. Corner stone of
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this being specialize struct page for such memory (see sections 5 to 7 of this
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document).
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This document is divided as follow, in the first section i expose the problems
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related to the use of a device specific allocator. The second section i expose
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the hardware limitations that are inherent to many platforms. The third section
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gives an overview of HMM designs. The fourth section explains how CPU page-
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table mirroring works and what is HMM purpose in this context. Fifth section
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deals with how device memory is represented inside the kernel. Finaly the last
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section present the new migration helper that allow to leverage the device DMA
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engine.
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HMM also provide optional helpers for SVM (Share Virtual Memory) ie allowing a
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device to transparently access program address coherently with the CPU meaning
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that any valid pointer on the CPU is also a valid pointer for the device. This
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is becoming a mandatory to simplify the use of advance heterogeneous computing
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where GPU, DSP, or FPGA are used to perform various computations on behalf of
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a process.
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This document is divided as follows: in the first section I expose the problems
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related to using device specific memory allocators. In the second section, I
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expose the hardware limitations that are inherent to many platforms. The third
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section gives an overview of the HMM design. The fourth section explains how
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CPU page-table mirroring works and what is HMM's purpose in this context. The
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fifth section deals with how device memory is represented inside the kernel.
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Finally, the last section presents a new migration helper that allows lever-
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aging the device DMA engine.
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1) Problems of using device specific memory allocator:
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2) System bus, device memory characteristics
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3) Share address space and migration
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1) Problems of using a device specific memory allocator:
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2) I/O bus, device memory characteristics
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3) Shared address space and migration
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4) Address space mirroring implementation and API
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5) Represent and manage device memory from core kernel point of view
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6) Migrate to and from device memory
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6) Migration to and from device memory
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7) Memory cgroup (memcg) and rss accounting
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-------------------------------------------------------------------------------
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1) Problems of using device specific memory allocator:
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1) Problems of using a device specific memory allocator:
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Device with large amount of on board memory (several giga bytes) like GPU have
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historically manage their memory through dedicated driver specific API. This
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creates a disconnect between memory allocated and managed by device driver and
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regular application memory (private anonymous, share memory or regular file
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back memory). From here on i will refer to this aspect as split address space.
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I use share address space to refer to the opposite situation ie one in which
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any memory region can be use by device transparently.
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Devices with a large amount of on board memory (several giga bytes) like GPUs
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have historically managed their memory through dedicated driver specific APIs.
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This creates a disconnect between memory allocated and managed by a device
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driver and regular application memory (private anonymous, shared memory, or
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regular file backed memory). From here on I will refer to this aspect as split
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address space. I use shared address space to refer to the opposite situation:
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i.e., one in which any application memory region can be used by a device
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transparently.
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Split address space because device can only access memory allocated through the
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device specific API. This imply that all memory object in a program are not
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equal from device point of view which complicate large program that rely on a
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wide set of libraries.
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device specific API. This implies that all memory objects in a program are not
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equal from the device point of view which complicates large programs that rely
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on a wide set of libraries.
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Concretly this means that code that wants to leverage device like GPU need to
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Concretly this means that code that wants to leverage devices like GPUs need to
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copy object between genericly allocated memory (malloc, mmap private/share/)
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and memory allocated through the device driver API (this still end up with an
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mmap but of the device file).
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For flat dataset (array, grid, image, ...) this isn't too hard to achieve but
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complex data-set (list, tree, ...) are hard to get right. Duplicating a complex
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data-set need to re-map all the pointer relations between each of its elements.
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This is error prone and program gets harder to debug because of the duplicate
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data-set.
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For flat data-sets (array, grid, image, ...) this isn't too hard to achieve but
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complex data-sets (list, tree, ...) are hard to get right. Duplicating a
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complex data-set needs to re-map all the pointer relations between each of its
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elements. This is error prone and program gets harder to debug because of the
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duplicate data-set and addresses.
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Split address space also means that library can not transparently use data they
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are getting from core program or other library and thus each library might have
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to duplicate its input data-set using specific memory allocator. Large project
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suffer from this and waste resources because of the various memory copy.
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Split address space also means that libraries can not transparently use data
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they are getting from the core program or another library and thus each library
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might have to duplicate its input data-set using the device specific memory
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allocator. Large projects suffer from this and waste resources because of the
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various memory copies.
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Duplicating each library API to accept as input or output memory allocted by
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each device specific allocator is not a viable option. It would lead to a
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combinatorial explosions in the library entry points.
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combinatorial explosion in the library entry points.
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Finaly with the advance of high level language constructs (in C++ but in other
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language too) it is now possible for compiler to leverage GPU or other devices
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without even the programmer knowledge. Some of compiler identified patterns are
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only do-able with a share address. It is as well more reasonable to use a share
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address space for all the other patterns.
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Finally, with the advance of high level language constructs (in C++ but in
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other languages too) it is now possible for the compiler to leverage GPUs and
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other devices without programmer knowledge. Some compiler identified patterns
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are only do-able with a shared address space. It is also more reasonable to use
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a shared address space for all other patterns.
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-------------------------------------------------------------------------------
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2) System bus, device memory characteristics
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2) I/O bus, device memory characteristics
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System bus cripple share address due to few limitations. Most system bus only
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I/O buses cripple shared address due to few limitations. Most I/O buses only
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allow basic memory access from device to main memory, even cache coherency is
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often optional. Access to device memory from CPU is even more limited, most
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often than not it is not cache coherent.
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often optional. Access to device memory from CPU is even more limited. More
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often than not, it is not cache coherent.
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If we only consider the PCIE bus than device can access main memory (often
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through an IOMMU) and be cache coherent with the CPUs. However it only allows
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a limited set of atomic operation from device on main memory. This is worse
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in the other direction the CPUs can only access a limited range of the device
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If we only consider the PCIE bus, then a device can access main memory (often
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through an IOMMU) and be cache coherent with the CPUs. However, it only allows
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a limited set of atomic operations from device on main memory. This is worse
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in the other direction, the CPU can only access a limited range of the device
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memory and can not perform atomic operations on it. Thus device memory can not
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be consider like regular memory from kernel point of view.
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be considered the same as regular memory from the kernel point of view.
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Another crippling factor is the limited bandwidth (~32GBytes/s with PCIE 4.0
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and 16 lanes). This is 33 times less that fastest GPU memory (1 TBytes/s).
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The final limitation is latency, access to main memory from the device has an
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order of magnitude higher latency than when the device access its own memory.
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and 16 lanes). This is 33 times less than the fastest GPU memory (1 TBytes/s).
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The final limitation is latency. Access to main memory from the device has an
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order of magnitude higher latency than when the device accesses its own memory.
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Some platform are developing new system bus or additions/modifications to PCIE
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to address some of those limitations (OpenCAPI, CCIX). They mainly allow two
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Some platforms are developing new I/O buses or additions/modifications to PCIE
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to address some of these limitations (OpenCAPI, CCIX). They mainly allow two
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way cache coherency between CPU and device and allow all atomic operations the
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architecture supports. Saddly not all platform are following this trends and
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some major architecture are left without hardware solutions to those problems.
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architecture supports. Saddly, not all platforms are following this trend and
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some major architectures are left without hardware solutions to these problems.
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So for share address space to make sense not only we must allow device to
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So for shared address space to make sense, not only must we allow device to
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access any memory memory but we must also permit any memory to be migrated to
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device memory while device is using it (blocking CPU access while it happens).
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-------------------------------------------------------------------------------
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3) Share address space and migration
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3) Shared address space and migration
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HMM intends to provide two main features. First one is to share the address
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space by duplication the CPU page table into the device page table so same
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address point to same memory and this for any valid main memory address in
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space by duplicating the CPU page table in the device page table so the same
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address points to the same physical memory for any valid main memory address in
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the process address space.
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To achieve this, HMM offer a set of helpers to populate the device page table
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To achieve this, HMM offers a set of helpers to populate the device page table
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while keeping track of CPU page table updates. Device page table updates are
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not as easy as CPU page table updates. To update the device page table you must
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allow a buffer (or use a pool of pre-allocated buffer) and write GPU specifics
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commands in it to perform the update (unmap, cache invalidations and flush,
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...). This can not be done through common code for all device. Hence why HMM
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provides helpers to factor out everything that can be while leaving the gory
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details to the device driver.
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not as easy as CPU page table updates. To update the device page table, you must
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allocate a buffer (or use a pool of pre-allocated buffers) and write GPU
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specific commands in it to perform the update (unmap, cache invalidations, and
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flush, ...). This can not be done through common code for all devices. Hence
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why HMM provides helpers to factor out everything that can be while leaving the
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hardware specific details to the device driver.
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The second mechanism HMM provide is a new kind of ZONE_DEVICE memory that does
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allow to allocate a struct page for each page of the device memory. Those page
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are special because the CPU can not map them. They however allow to migrate
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main memory to device memory using exhisting migration mechanism and everything
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looks like if page was swap out to disk from CPU point of view. Using a struct
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page gives the easiest and cleanest integration with existing mm mechanisms.
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Again here HMM only provide helpers, first to hotplug new ZONE_DEVICE memory
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for the device memory and second to perform migration. Policy decision of what
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and when to migrate things is left to the device driver.
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The second mechanism HMM provides, is a new kind of ZONE_DEVICE memory that
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allows allocating a struct page for each page of the device memory. Those pages
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are special because the CPU can not map them. However, they allow migrating
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main memory to device memory using existing migration mechanisms and everything
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looks like a page is swapped out to disk from the CPU point of view. Using a
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struct page gives the easiest and cleanest integration with existing mm mech-
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anisms. Here again, HMM only provides helpers, first to hotplug new ZONE_DEVICE
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memory for the device memory and second to perform migration. Policy decisions
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of what and when to migrate things is left to the device driver.
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Note that any CPU access to a device page trigger a page fault and a migration
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back to main memory ie when a page backing an given address A is migrated from
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a main memory page to a device page then any CPU access to address A trigger a
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page fault and initiate a migration back to main memory.
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Note that any CPU access to a device page triggers a page fault and a migration
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back to main memory. For example, when a page backing a given CPU address A is
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migrated from a main memory page to a device page, then any CPU access to
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address A triggers a page fault and initiates a migration back to main memory.
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With this two features, HMM not only allow a device to mirror a process address
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space and keeps both CPU and device page table synchronize, but also allow to
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leverage device memory by migrating part of data-set that is actively use by a
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device.
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With these two features, HMM not only allows a device to mirror process address
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space and keeping both CPU and device page table synchronized, but also lever-
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ages device memory by migrating the part of the data-set that is actively being
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used by the device.
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-------------------------------------------------------------------------------
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4) Address space mirroring implementation and API
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Address space mirroring main objective is to allow to duplicate range of CPU
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page table into a device page table and HMM helps keeping both synchronize. A
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Address space mirroring's main objective is to allow duplication of a range of
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CPU page table into a device page table; HMM helps keep both synchronized. A
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device driver that want to mirror a process address space must start with the
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registration of an hmm_mirror struct:
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@ -155,8 +163,8 @@ registration of an hmm_mirror struct:
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struct mm_struct *mm);
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The locked variant is to be use when the driver is already holding the mmap_sem
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of the mm in write mode. The mirror struct has a set of callback that are use
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to propagate CPU page table:
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of the mm in write mode. The mirror struct has a set of callbacks that are used
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to propagate CPU page tables:
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struct hmm_mirror_ops {
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/* sync_cpu_device_pagetables() - synchronize page tables
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@ -181,13 +189,13 @@ to propagate CPU page table:
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unsigned long end);
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};
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Device driver must perform update to the range following action (turn range
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read only, or fully unmap, ...). Once driver callback returns the device must
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be done with the update.
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The device driver must perform the update action to the range (mark range
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read only, or fully unmap, ...). The device must be done with the update before
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the driver callback returns.
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When device driver wants to populate a range of virtual address it can use
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either:
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When the device driver wants to populate a range of virtual addresses, it can
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use either:
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int hmm_vma_get_pfns(struct vm_area_struct *vma,
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struct hmm_range *range,
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unsigned long start,
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@ -201,17 +209,19 @@ either:
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bool write,
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bool block);
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First one (hmm_vma_get_pfns()) will only fetch present CPU page table entry and
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will not trigger a page fault on missing or non present entry. The second one
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do trigger page fault on missing or read only entry if write parameter is true.
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Page fault use the generic mm page fault code path just like a CPU page fault.
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The first one (hmm_vma_get_pfns()) will only fetch present CPU page table
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entries and will not trigger a page fault on missing or non present entries.
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The second one does trigger a page fault on missing or read only entry if the
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write parameter is true. Page faults use the generic mm page fault code path
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just like a CPU page fault.
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Both function copy CPU page table into their pfns array argument. Each entry in
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that array correspond to an address in the virtual range. HMM provide a set of
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flags to help driver identify special CPU page table entries.
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Both functions copy CPU page table entries into their pfns array argument. Each
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entry in that array corresponds to an address in the virtual range. HMM
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provides a set of flags to help the driver identify special CPU page table
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entries.
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Locking with the update() callback is the most important aspect the driver must
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respect in order to keep things properly synchronize. The usage pattern is :
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respect in order to keep things properly synchronized. The usage pattern is:
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int driver_populate_range(...)
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{
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@ -233,43 +243,44 @@ respect in order to keep things properly synchronize. The usage pattern is :
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return 0;
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}
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The driver->update lock is the same lock that driver takes inside its update()
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callback. That lock must be call before hmm_vma_range_done() to avoid any race
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with a concurrent CPU page table update.
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The driver->update lock is the same lock that the driver takes inside its
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update() callback. That lock must be held before hmm_vma_range_done() to avoid
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any race with a concurrent CPU page table update.
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HMM implements all this on top of the mmu_notifier API because we wanted to a
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simpler API and also to be able to perform optimization latter own like doing
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concurrent device update in multi-devices scenario.
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HMM implements all this on top of the mmu_notifier API because we wanted a
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simpler API and also to be able to perform optimizations latter on like doing
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concurrent device updates in multi-devices scenario.
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HMM also serve as an impedence missmatch between how CPU page table update are
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done (by CPU write to the page table and TLB flushes) from how device update
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their own page table. Device update is a multi-step process, first appropriate
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commands are write to a buffer, then this buffer is schedule for execution on
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the device. It is only once the device has executed commands in the buffer that
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the update is done. Creating and scheduling update command buffer can happen
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concurrently for multiple devices. Waiting for each device to report commands
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as executed is serialize (there is no point in doing this concurrently).
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HMM also serves as an impedence mismatch between how CPU page table updates
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are done (by CPU write to the page table and TLB flushes) and how devices
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update their own page table. Device updates are a multi-step process. First,
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appropriate commands are writen to a buffer, then this buffer is scheduled for
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execution on the device. It is only once the device has executed commands in
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the buffer that the update is done. Creating and scheduling the update command
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buffer can happen concurrently for multiple devices. Waiting for each device to
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report commands as executed is serialized (there is no point in doing this
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concurrently).
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-------------------------------------------------------------------------------
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5) Represent and manage device memory from core kernel point of view
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Several differents design were try to support device memory. First one use
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device specific data structure to keep information about migrated memory and
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HMM hooked itself in various place of mm code to handle any access to address
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that were back by device memory. It turns out that this ended up replicating
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most of the fields of struct page and also needed many kernel code path to be
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updated to understand this new kind of memory.
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Several different designs were tried to support device memory. First one used
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a device specific data structure to keep information about migrated memory and
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HMM hooked itself in various places of mm code to handle any access to
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addresses that were backed by device memory. It turns out that this ended up
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replicating most of the fields of struct page and also needed many kernel code
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paths to be updated to understand this new kind of memory.
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Thing is most kernel code path never try to access the memory behind a page
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but only care about struct page contents. Because of this HMM switchted to
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directly using struct page for device memory which left most kernel code path
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un-aware of the difference. We only need to make sure that no one ever try to
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map those page from the CPU side.
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Most kernel code paths never try to access the memory behind a page
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but only care about struct page contents. Because of this, HMM switched to
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directly using struct page for device memory which left most kernel code paths
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unaware of the difference. We only need to make sure that no one ever tries to
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map those pages from the CPU side.
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HMM provide a set of helpers to register and hotplug device memory as a new
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region needing struct page. This is offer through a very simple API:
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HMM provides a set of helpers to register and hotplug device memory as a new
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region needing a struct page. This is offered through a very simple API:
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struct hmm_devmem *hmm_devmem_add(const struct hmm_devmem_ops *ops,
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struct device *device,
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@ -289,18 +300,19 @@ The hmm_devmem_ops is where most of the important things are:
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};
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The first callback (free()) happens when the last reference on a device page is
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drop. This means the device page is now free and no longer use by anyone. The
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second callback happens whenever CPU try to access a device page which it can
|
||||
not do. This second callback must trigger a migration back to system memory.
|
||||
dropped. This means the device page is now free and no longer used by anyone.
|
||||
The second callback happens whenever the CPU tries to access a device page
|
||||
which it can not do. This second callback must trigger a migration back to
|
||||
system memory.
|
||||
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
6) Migrate to and from device memory
|
||||
6) Migration to and from device memory
|
||||
|
||||
Because CPU can not access device memory, migration must use device DMA engine
|
||||
to perform copy from and to device memory. For this we need a new migration
|
||||
helper:
|
||||
Because the CPU can not access device memory, migration must use the device DMA
|
||||
engine to perform copy from and to device memory. For this we need a new
|
||||
migration helper:
|
||||
|
||||
int migrate_vma(const struct migrate_vma_ops *ops,
|
||||
struct vm_area_struct *vma,
|
||||
@ -311,15 +323,15 @@ helper:
|
||||
unsigned long *dst,
|
||||
void *private);
|
||||
|
||||
Unlike other migration function it works on a range of virtual address, there
|
||||
is two reasons for that. First device DMA copy has a high setup overhead cost
|
||||
Unlike other migration functions it works on a range of virtual address, there
|
||||
are two reasons for that. First, device DMA copy has a high setup overhead cost
|
||||
and thus batching multiple pages is needed as otherwise the migration overhead
|
||||
make the whole excersie pointless. The second reason is because driver trigger
|
||||
such migration base on range of address the device is actively accessing.
|
||||
makes the whole exersize pointless. The second reason is because the
|
||||
migration might be for a range of addresses the device is actively accessing.
|
||||
|
||||
The migrate_vma_ops struct define two callbacks. First one (alloc_and_copy())
|
||||
control destination memory allocation and copy operation. Second one is there
|
||||
to allow device driver to perform cleanup operation after migration.
|
||||
The migrate_vma_ops struct defines two callbacks. First one (alloc_and_copy())
|
||||
controls destination memory allocation and copy operation. Second one is there
|
||||
to allow the device driver to perform cleanup operations after migration.
|
||||
|
||||
struct migrate_vma_ops {
|
||||
void (*alloc_and_copy)(struct vm_area_struct *vma,
|
||||
@ -336,19 +348,19 @@ to allow device driver to perform cleanup operation after migration.
|
||||
void *private);
|
||||
};
|
||||
|
||||
It is important to stress that this migration helpers allow for hole in the
|
||||
It is important to stress that these migration helpers allow for holes in the
|
||||
virtual address range. Some pages in the range might not be migrated for all
|
||||
the usual reasons (page is pin, page is lock, ...). This helper does not fail
|
||||
but just skip over those pages.
|
||||
the usual reasons (page is pinned, page is locked, ...). This helper does not
|
||||
fail but just skips over those pages.
|
||||
|
||||
The alloc_and_copy() might as well decide to not migrate all pages in the
|
||||
range (for reasons under the callback control). For those the callback just
|
||||
have to leave the corresponding dst entry empty.
|
||||
The alloc_and_copy() might decide to not migrate all pages in the
|
||||
range (for reasons under the callback control). For those, the callback just
|
||||
has to leave the corresponding dst entry empty.
|
||||
|
||||
Finaly the migration of the struct page might fails (for file back page) for
|
||||
Finally, the migration of the struct page might fail (for file backed page) for
|
||||
various reasons (failure to freeze reference, or update page cache, ...). If
|
||||
that happens then the finalize_and_map() can catch any pages that was not
|
||||
migrated. Note those page were still copied to new page and thus we wasted
|
||||
that happens, then the finalize_and_map() can catch any pages that were not
|
||||
migrated. Note those pages were still copied to a new page and thus we wasted
|
||||
bandwidth but this is considered as a rare event and a price that we are
|
||||
willing to pay to keep all the code simpler.
|
||||
|
||||
@ -358,27 +370,27 @@ willing to pay to keep all the code simpler.
|
||||
7) Memory cgroup (memcg) and rss accounting
|
||||
|
||||
For now device memory is accounted as any regular page in rss counters (either
|
||||
anonymous if device page is use for anonymous, file if device page is use for
|
||||
file back page or shmem if device page is use for share memory). This is a
|
||||
deliberate choice to keep existing application that might start using device
|
||||
memory without knowing about it to keep runing unimpacted.
|
||||
anonymous if device page is used for anonymous, file if device page is used for
|
||||
file backed page or shmem if device page is used for shared memory). This is a
|
||||
deliberate choice to keep existing applications, that might start using device
|
||||
memory without knowing about it, running unimpacted.
|
||||
|
||||
Drawbacks is that OOM killer might kill an application using a lot of device
|
||||
memory and not a lot of regular system memory and thus not freeing much system
|
||||
memory. We want to gather more real world experience on how application and
|
||||
system react under memory pressure in the presence of device memory before
|
||||
A Drawback is that the OOM killer might kill an application using a lot of
|
||||
device memory and not a lot of regular system memory and thus not freeing much
|
||||
system memory. We want to gather more real world experience on how applications
|
||||
and system react under memory pressure in the presence of device memory before
|
||||
deciding to account device memory differently.
|
||||
|
||||
|
||||
Same decision was made for memory cgroup. Device memory page are accounted
|
||||
Same decision was made for memory cgroup. Device memory pages are accounted
|
||||
against same memory cgroup a regular page would be accounted to. This does
|
||||
simplify migration to and from device memory. This also means that migration
|
||||
back from device memory to regular memory can not fail because it would
|
||||
go above memory cgroup limit. We might revisit this choice latter on once we
|
||||
get more experience in how device memory is use and its impact on memory
|
||||
get more experience in how device memory is used and its impact on memory
|
||||
resource control.
|
||||
|
||||
|
||||
Note that device memory can never be pin nor by device driver nor through GUP
|
||||
Note that device memory can never be pinned by device driver nor through GUP
|
||||
and thus such memory is always free upon process exit. Or when last reference
|
||||
is drop in case of share memory or file back memory.
|
||||
is dropped in case of shared memory or file backed memory.
|
||||
|
||||
@ -6410,6 +6410,7 @@ L: linux-mm@kvack.org
|
||||
S: Maintained
|
||||
F: mm/hmm*
|
||||
F: include/linux/hmm*
|
||||
F: Documentation/vm/hmm.txt
|
||||
|
||||
HOST AP DRIVER
|
||||
M: Jouni Malinen <j@w1.fi>
|
||||
|
||||
Loading…
Reference in New Issue
Block a user