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drm/amdgpu: add smu v13.0.6 pcs xgmi ras error query support
add pcs xgmi ras error query support for smu v13.0.6. Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -54,6 +54,7 @@ enum amdgpu_mca_ip {
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AMDGPU_MCA_IP_SMU,
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AMDGPU_MCA_IP_MP5,
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AMDGPU_MCA_IP_UMC,
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AMDGPU_MCA_IP_PCS_XGMI,
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AMDGPU_MCA_IP_COUNT,
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};
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@ -2379,6 +2379,7 @@ static const struct mca_bank_ipid smu_v13_0_6_mca_ipid_table[AMDGPU_MCA_IP_COUNT
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MCA_BANK_IPID(UMC, 0x96, 0x0),
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MCA_BANK_IPID(SMU, 0x01, 0x1),
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MCA_BANK_IPID(MP5, 0x01, 0x2),
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MCA_BANK_IPID(PCS_XGMI, 0x50, 0x0),
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};
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static void mca_bank_entry_info_decode(struct mca_bank_entry *entry, struct mca_bank_info *info)
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@ -2482,6 +2483,22 @@ static int mca_umc_mca_get_err_count(const struct mca_ras_info *mca_ras, struct
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return 0;
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}
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static int mca_pcs_xgmi_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
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enum amdgpu_mca_error_type type, struct mca_bank_entry *entry,
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uint32_t *count)
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{
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u32 ext_error_code;
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ext_error_code = MCA_REG__STATUS__ERRORCODEEXT(entry->regs[MCA_REG_IDX_STATUS]);
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if (type == AMDGPU_MCA_ERROR_TYPE_UE && ext_error_code == 0)
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*count = 1;
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else if (type == AMDGPU_MCA_ERROR_TYPE_CE && ext_error_code == 6)
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*count = 1;
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return 0;
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}
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static bool mca_smu_check_error_code(struct amdgpu_device *adev, const struct mca_ras_info *mca_ras,
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uint32_t errcode)
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{
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@ -2609,6 +2626,10 @@ static const struct mca_ras_info mca_ras_table[] = {
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.err_code_count = ARRAY_SIZE(mmhub_err_codes),
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.get_err_count = mca_smu_mca_get_err_count,
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.bank_is_valid = mca_smu_bank_is_valid,
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}, {
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.blkid = AMDGPU_RAS_BLOCK__XGMI_WAFL,
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.ip = AMDGPU_MCA_IP_PCS_XGMI,
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.get_err_count = mca_pcs_xgmi_mca_get_err_count,
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},
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};
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