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drm/i915: Fix VIDEO_DIP_CTL bit shifts

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The shifts for VSC_SELECT bits are wrong, fix it. Good thing is the
definitions are unused.

v2: Moves definitions in another patch (Manasi)
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Fixes: 7af2be6d54 ("drm/i915/icl: Add VIDEO_DIP registers")
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181005185643.31660-1-dhinakaran.pandiyan@intel.com
(cherry picked from commit 0920966261)
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
This commit is contained in:
Dhinakaran Pandiyan 2018-10-05 11:56:42 -07:00 committed by Joonas Lahtinen
parent 2c2f6e30d5
commit 76271ef263
1 changed files with 6 additions and 6 deletions
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12
drivers/gpu/drm/i915/i915_reg.h
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@ -4593,12 +4593,12 @@ enum {
#define DRM_DIP_ENABLE (1 << 28)
#define PSR_VSC_BIT_7_SET (1 << 27)
#define VSC_SELECT_MASK (0x3 << 26)
#define VSC_SELECT_SHIFT 26
#define VSC_DIP_HW_HEA_DATA (0 << 26)
#define VSC_DIP_HW_HEA_SW_DATA (1 << 26)
#define VSC_DIP_HW_DATA_SW_HEA (2 << 26)
#define VSC_DIP_SW_HEA_DATA (3 << 26)
#define VSC_SELECT_MASK (0x3 << 25)
#define VSC_SELECT_SHIFT 25
#define VSC_DIP_HW_HEA_DATA (0 << 25)
#define VSC_DIP_HW_HEA_SW_DATA (1 << 25)
#define VSC_DIP_HW_DATA_SW_HEA (2 << 25)
#define VSC_DIP_SW_HEA_DATA (3 << 25)
#define VDIP_ENABLE_PPS (1 << 24)
/* Panel power sequencing */