mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
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drm/nouveau/mpeg: convert to new-style nvkm_engine
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
parent
6f41c7c569
commit
7624fc011e
@ -19,8 +19,6 @@ struct nvkm_engine {
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struct list_head contexts;
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spinlock_t lock;
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void (*tile_prog)(struct nvkm_engine *, int region);
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};
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struct nvkm_engine_func {
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@ -1,38 +1,9 @@
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#ifndef __NVKM_MPEG_H__
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#define __NVKM_MPEG_H__
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#include <core/engine.h>
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struct nvkm_mpeg {
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struct nvkm_engine engine;
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};
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#define nvkm_mpeg_create(p,e,c,d) \
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nvkm_engine_create((p), (e), (c), true, "PMPEG", "mpeg", (d))
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#define nvkm_mpeg_destroy(d) \
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nvkm_engine_destroy(&(d)->engine)
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#define nvkm_mpeg_init(d) \
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nvkm_engine_init_old(&(d)->engine)
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#define nvkm_mpeg_fini(d,s) \
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nvkm_engine_fini_old(&(d)->engine, (s))
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#define _nvkm_mpeg_dtor _nvkm_engine_dtor
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#define _nvkm_mpeg_init _nvkm_engine_init
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#define _nvkm_mpeg_fini _nvkm_engine_fini
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extern struct nvkm_oclass nv31_mpeg_oclass;
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extern struct nvkm_oclass nv40_mpeg_oclass;
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extern struct nvkm_oclass nv44_mpeg_oclass;
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extern struct nvkm_oclass nv50_mpeg_oclass;
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extern struct nvkm_oclass g84_mpeg_oclass;
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extern struct nvkm_oclass nv40_mpeg_sclass[];
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void nv31_mpeg_intr(struct nvkm_subdev *);
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void nv31_mpeg_tile_prog(struct nvkm_engine *, int);
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int nv31_mpeg_init(struct nvkm_object *);
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extern struct nvkm_ofuncs nv50_mpeg_ofuncs;
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int nv50_mpeg_context_ctor(struct nvkm_object *, struct nvkm_object *,
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struct nvkm_oclass *, void *, u32,
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struct nvkm_object **);
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void nv50_mpeg_intr(struct nvkm_subdev *);
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int nv50_mpeg_init(struct nvkm_object *);
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int nv31_mpeg_new(struct nvkm_device *, int index, struct nvkm_engine **);
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int nv40_mpeg_new(struct nvkm_device *, int index, struct nvkm_engine **);
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int nv44_mpeg_new(struct nvkm_device *, int index, struct nvkm_engine **);
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int nv50_mpeg_new(struct nvkm_device *, int index, struct nvkm_engine **);
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int g84_mpeg_new(struct nvkm_device *, int index, struct nvkm_engine **);
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#endif
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@ -381,7 +381,7 @@ nv31_chipset = {
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.dma = nv04_dma_new,
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.fifo = nv17_fifo_new,
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.gr = nv30_gr_new,
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// .mpeg = nv31_mpeg_new,
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.mpeg = nv31_mpeg_new,
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.sw = nv10_sw_new,
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};
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@ -403,7 +403,7 @@ nv34_chipset = {
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.dma = nv04_dma_new,
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.fifo = nv17_fifo_new,
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.gr = nv34_gr_new,
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// .mpeg = nv31_mpeg_new,
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.mpeg = nv31_mpeg_new,
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.sw = nv10_sw_new,
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};
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@ -446,7 +446,7 @@ nv36_chipset = {
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.dma = nv04_dma_new,
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.fifo = nv17_fifo_new,
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.gr = nv35_gr_new,
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// .mpeg = nv31_mpeg_new,
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.mpeg = nv31_mpeg_new,
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.sw = nv10_sw_new,
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};
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@ -470,7 +470,7 @@ nv40_chipset = {
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.dma = nv04_dma_new,
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.fifo = nv40_fifo_new,
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.gr = nv40_gr_new,
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// .mpeg = nv40_mpeg_new,
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.mpeg = nv40_mpeg_new,
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.pm = nv40_pm_new,
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.sw = nv10_sw_new,
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};
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@ -495,7 +495,7 @@ nv41_chipset = {
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.dma = nv04_dma_new,
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.fifo = nv40_fifo_new,
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.gr = nv40_gr_new,
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// .mpeg = nv40_mpeg_new,
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.mpeg = nv40_mpeg_new,
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.pm = nv40_pm_new,
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.sw = nv10_sw_new,
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};
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@ -520,7 +520,7 @@ nv42_chipset = {
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.dma = nv04_dma_new,
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.fifo = nv40_fifo_new,
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.gr = nv40_gr_new,
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// .mpeg = nv40_mpeg_new,
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.mpeg = nv40_mpeg_new,
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.pm = nv40_pm_new,
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.sw = nv10_sw_new,
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};
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@ -545,7 +545,7 @@ nv43_chipset = {
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.dma = nv04_dma_new,
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.fifo = nv40_fifo_new,
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.gr = nv40_gr_new,
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// .mpeg = nv40_mpeg_new,
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.mpeg = nv40_mpeg_new,
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.pm = nv40_pm_new,
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.sw = nv10_sw_new,
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};
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@ -570,7 +570,7 @@ nv44_chipset = {
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.dma = nv04_dma_new,
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.fifo = nv40_fifo_new,
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.gr = nv44_gr_new,
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// .mpeg = nv44_mpeg_new,
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.mpeg = nv44_mpeg_new,
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.pm = nv40_pm_new,
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.sw = nv10_sw_new,
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};
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@ -595,7 +595,7 @@ nv45_chipset = {
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.dma = nv04_dma_new,
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.fifo = nv40_fifo_new,
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.gr = nv40_gr_new,
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// .mpeg = nv44_mpeg_new,
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.mpeg = nv44_mpeg_new,
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.pm = nv40_pm_new,
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.sw = nv10_sw_new,
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};
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@ -620,7 +620,7 @@ nv46_chipset = {
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.dma = nv04_dma_new,
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.fifo = nv40_fifo_new,
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.gr = nv44_gr_new,
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// .mpeg = nv44_mpeg_new,
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.mpeg = nv44_mpeg_new,
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.pm = nv40_pm_new,
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.sw = nv10_sw_new,
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};
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@ -645,7 +645,7 @@ nv47_chipset = {
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.dma = nv04_dma_new,
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.fifo = nv40_fifo_new,
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.gr = nv40_gr_new,
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// .mpeg = nv44_mpeg_new,
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.mpeg = nv44_mpeg_new,
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.pm = nv40_pm_new,
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.sw = nv10_sw_new,
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};
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@ -670,7 +670,7 @@ nv49_chipset = {
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.dma = nv04_dma_new,
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.fifo = nv40_fifo_new,
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.gr = nv40_gr_new,
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// .mpeg = nv44_mpeg_new,
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.mpeg = nv44_mpeg_new,
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.pm = nv40_pm_new,
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.sw = nv10_sw_new,
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};
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@ -695,7 +695,7 @@ nv4a_chipset = {
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.dma = nv04_dma_new,
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.fifo = nv40_fifo_new,
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.gr = nv44_gr_new,
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// .mpeg = nv44_mpeg_new,
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.mpeg = nv44_mpeg_new,
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.pm = nv40_pm_new,
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.sw = nv10_sw_new,
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};
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@ -720,7 +720,7 @@ nv4b_chipset = {
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.dma = nv04_dma_new,
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.fifo = nv40_fifo_new,
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.gr = nv40_gr_new,
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// .mpeg = nv44_mpeg_new,
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.mpeg = nv44_mpeg_new,
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.pm = nv40_pm_new,
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.sw = nv10_sw_new,
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};
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@ -745,7 +745,7 @@ nv4c_chipset = {
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.dma = nv04_dma_new,
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.fifo = nv40_fifo_new,
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.gr = nv44_gr_new,
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// .mpeg = nv44_mpeg_new,
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.mpeg = nv44_mpeg_new,
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.pm = nv40_pm_new,
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.sw = nv10_sw_new,
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};
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@ -770,7 +770,7 @@ nv4e_chipset = {
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.dma = nv04_dma_new,
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.fifo = nv40_fifo_new,
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.gr = nv44_gr_new,
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// .mpeg = nv44_mpeg_new,
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.mpeg = nv44_mpeg_new,
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.pm = nv40_pm_new,
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.sw = nv10_sw_new,
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};
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@ -798,7 +798,7 @@ nv50_chipset = {
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.dma = nv50_dma_new,
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.fifo = nv50_fifo_new,
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.gr = nv50_gr_new,
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// .mpeg = nv50_mpeg_new,
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.mpeg = nv50_mpeg_new,
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.pm = nv50_pm_new,
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.sw = nv50_sw_new,
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};
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@ -823,7 +823,7 @@ nv63_chipset = {
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.dma = nv04_dma_new,
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.fifo = nv40_fifo_new,
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.gr = nv44_gr_new,
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// .mpeg = nv44_mpeg_new,
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.mpeg = nv44_mpeg_new,
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.pm = nv40_pm_new,
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.sw = nv10_sw_new,
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};
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@ -848,7 +848,7 @@ nv67_chipset = {
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.dma = nv04_dma_new,
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.fifo = nv40_fifo_new,
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.gr = nv44_gr_new,
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// .mpeg = nv44_mpeg_new,
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.mpeg = nv44_mpeg_new,
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.pm = nv40_pm_new,
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.sw = nv10_sw_new,
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};
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@ -873,7 +873,7 @@ nv68_chipset = {
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.dma = nv04_dma_new,
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.fifo = nv40_fifo_new,
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.gr = nv44_gr_new,
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// .mpeg = nv44_mpeg_new,
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.mpeg = nv44_mpeg_new,
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.pm = nv40_pm_new,
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.sw = nv10_sw_new,
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};
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@ -903,7 +903,7 @@ nv84_chipset = {
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.dma = nv50_dma_new,
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.fifo = g84_fifo_new,
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.gr = g84_gr_new,
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// .mpeg = g84_mpeg_new,
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.mpeg = g84_mpeg_new,
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.pm = g84_pm_new,
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.sw = nv50_sw_new,
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.vp = g84_vp_new,
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@ -934,7 +934,7 @@ nv86_chipset = {
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.dma = nv50_dma_new,
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.fifo = g84_fifo_new,
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.gr = g84_gr_new,
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// .mpeg = g84_mpeg_new,
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.mpeg = g84_mpeg_new,
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.pm = g84_pm_new,
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.sw = nv50_sw_new,
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.vp = g84_vp_new,
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@ -965,7 +965,7 @@ nv92_chipset = {
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.dma = nv50_dma_new,
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.fifo = g84_fifo_new,
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.gr = g84_gr_new,
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// .mpeg = g84_mpeg_new,
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.mpeg = g84_mpeg_new,
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.pm = g84_pm_new,
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.sw = nv50_sw_new,
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.vp = g84_vp_new,
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@ -996,7 +996,7 @@ nv94_chipset = {
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.dma = nv50_dma_new,
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.fifo = g84_fifo_new,
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.gr = g84_gr_new,
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// .mpeg = g84_mpeg_new,
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.mpeg = g84_mpeg_new,
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.pm = g84_pm_new,
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.sw = nv50_sw_new,
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.vp = g84_vp_new,
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@ -1025,7 +1025,7 @@ nv96_chipset = {
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.fifo = g84_fifo_new,
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.gr = g84_gr_new,
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.gr = nv50_gr_new,
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// .mpeg = g84_mpeg_new,
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.mpeg = g84_mpeg_new,
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.vp = g84_vp_new,
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.cipher = g84_cipher_new,
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.bsp = g84_bsp_new,
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@ -1089,7 +1089,7 @@ nva0_chipset = {
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.dma = nv50_dma_new,
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.fifo = g84_fifo_new,
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.gr = gt200_gr_new,
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// .mpeg = g84_mpeg_new,
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.mpeg = g84_mpeg_new,
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.pm = gt200_pm_new,
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.sw = nv50_sw_new,
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.vp = g84_vp_new,
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@ -1120,7 +1120,7 @@ nva3_chipset = {
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.dma = nv50_dma_new,
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.fifo = g84_fifo_new,
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.gr = gt215_gr_new,
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// .mpeg = g84_mpeg_new,
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.mpeg = g84_mpeg_new,
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.mspdec = gt215_mspdec_new,
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.msppp = gt215_msppp_new,
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.msvld = gt215_msvld_new,
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@ -32,13 +32,10 @@ nv30_identify(struct nvkm_device *device)
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case 0x35:
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break;
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case 0x31:
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device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
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break;
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case 0x36:
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device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
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break;
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case 0x34:
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device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
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break;
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default:
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return -EINVAL;
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@ -28,52 +28,36 @@ nv40_identify(struct nvkm_device *device)
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{
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switch (device->chipset) {
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case 0x40:
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device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
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break;
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case 0x41:
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device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
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break;
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case 0x42:
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device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
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break;
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case 0x43:
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device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
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break;
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case 0x45:
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device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
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break;
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case 0x47:
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device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
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break;
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case 0x49:
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device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
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break;
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case 0x4b:
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device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
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break;
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case 0x44:
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device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
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break;
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case 0x46:
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device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
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break;
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case 0x4a:
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device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
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break;
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case 0x4c:
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device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
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break;
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case 0x4e:
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device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
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break;
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case 0x63:
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device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
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break;
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case 0x67:
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device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
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break;
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case 0x68:
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device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
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break;
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default:
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return -EINVAL;
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@ -28,34 +28,26 @@ nv50_identify(struct nvkm_device *device)
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{
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switch (device->chipset) {
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case 0x50:
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device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass;
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break;
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case 0x84:
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device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
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break;
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case 0x86:
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device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
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break;
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case 0x92:
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device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
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break;
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case 0x94:
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device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
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break;
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case 0x96:
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device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
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break;
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case 0x98:
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break;
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case 0xa0:
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device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
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break;
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case 0xaa:
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break;
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case 0xac:
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break;
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case 0xa3:
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device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
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break;
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case 0xa5:
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break;
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@ -27,6 +27,8 @@
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static const struct nvkm_engine_func
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g84_mpeg = {
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.init = nv50_mpeg_init,
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.intr = nv50_mpeg_intr,
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.cclass = &nv50_mpeg_cclass,
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.sclass = {
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{ -1, -1, G82_MPEG, &nv31_mpeg_object },
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@ -34,33 +36,9 @@ g84_mpeg = {
|
||||
}
|
||||
};
|
||||
|
||||
static int
|
||||
g84_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
||||
struct nvkm_oclass *oclass, void *data, u32 size,
|
||||
struct nvkm_object **pobject)
|
||||
int
|
||||
g84_mpeg_new(struct nvkm_device *device, int index, struct nvkm_engine **pmpeg)
|
||||
{
|
||||
struct nvkm_mpeg *mpeg;
|
||||
int ret;
|
||||
|
||||
ret = nvkm_mpeg_create(parent, engine, oclass, &mpeg);
|
||||
*pobject = nv_object(mpeg);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
mpeg->engine.func = &g84_mpeg;
|
||||
|
||||
nv_subdev(mpeg)->unit = 0x00000002;
|
||||
nv_subdev(mpeg)->intr = nv50_mpeg_intr;
|
||||
return 0;
|
||||
return nvkm_engine_new_(&g84_mpeg, device, index, 0x00000002,
|
||||
true, pmpeg);
|
||||
}
|
||||
|
||||
struct nvkm_oclass
|
||||
g84_mpeg_oclass = {
|
||||
.handle = NV_ENGINE(MPEG, 0x84),
|
||||
.ofuncs = &(struct nvkm_ofuncs) {
|
||||
.ctor = g84_mpeg_ctor,
|
||||
.dtor = _nvkm_mpeg_dtor,
|
||||
.init = nv50_mpeg_init,
|
||||
.fini = _nvkm_mpeg_fini,
|
||||
},
|
||||
};
|
||||
|
@ -68,10 +68,10 @@ nv31_mpeg_chan_dtor(struct nvkm_object *object)
|
||||
struct nv31_mpeg *mpeg = chan->mpeg;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&mpeg->base.engine.lock, flags);
|
||||
spin_lock_irqsave(&mpeg->engine.lock, flags);
|
||||
if (mpeg->chan == chan)
|
||||
mpeg->chan = NULL;
|
||||
spin_unlock_irqrestore(&mpeg->base.engine.lock, flags);
|
||||
spin_unlock_irqrestore(&mpeg->engine.lock, flags);
|
||||
return chan;
|
||||
}
|
||||
|
||||
@ -97,12 +97,12 @@ nv31_mpeg_chan_new(struct nvkm_fifo_chan *fifoch,
|
||||
chan->fifo = fifoch;
|
||||
*pobject = &chan->object;
|
||||
|
||||
spin_lock_irqsave(&mpeg->base.engine.lock, flags);
|
||||
spin_lock_irqsave(&mpeg->engine.lock, flags);
|
||||
if (!mpeg->chan) {
|
||||
mpeg->chan = chan;
|
||||
ret = 0;
|
||||
}
|
||||
spin_unlock_irqrestore(&mpeg->base.engine.lock, flags);
|
||||
spin_unlock_irqrestore(&mpeg->engine.lock, flags);
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -111,11 +111,10 @@ nv31_mpeg_chan_new(struct nvkm_fifo_chan *fifoch,
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
nv31_mpeg_tile_prog(struct nvkm_engine *engine, int i)
|
||||
nv31_mpeg_tile(struct nvkm_engine *engine, int i, struct nvkm_fb_tile *tile)
|
||||
{
|
||||
struct nv31_mpeg *mpeg = (void *)engine;
|
||||
struct nvkm_device *device = mpeg->base.engine.subdev.device;
|
||||
struct nvkm_fb_tile *tile = &device->fb->tile.region[i];
|
||||
struct nv31_mpeg *mpeg = nv31_mpeg(engine);
|
||||
struct nvkm_device *device = mpeg->engine.subdev.device;
|
||||
|
||||
nvkm_wr32(device, 0x00b008 + (i * 0x10), tile->pitch);
|
||||
nvkm_wr32(device, 0x00b004 + (i * 0x10), tile->limit);
|
||||
@ -164,23 +163,24 @@ nv31_mpeg_mthd_dma(struct nvkm_device *device, u32 mthd, u32 data)
|
||||
static bool
|
||||
nv31_mpeg_mthd(struct nv31_mpeg *mpeg, u32 mthd, u32 data)
|
||||
{
|
||||
struct nvkm_device *device = mpeg->base.engine.subdev.device;
|
||||
struct nvkm_device *device = mpeg->engine.subdev.device;
|
||||
switch (mthd) {
|
||||
case 0x190:
|
||||
case 0x1a0:
|
||||
case 0x1b0:
|
||||
return mpeg->mthd_dma(device, mthd, data);
|
||||
return mpeg->func->mthd_dma(device, mthd, data);
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
void
|
||||
nv31_mpeg_intr(struct nvkm_subdev *subdev)
|
||||
static void
|
||||
nv31_mpeg_intr(struct nvkm_engine *engine)
|
||||
{
|
||||
struct nv31_mpeg *mpeg = (void *)subdev;
|
||||
struct nvkm_device *device = mpeg->base.engine.subdev.device;
|
||||
struct nv31_mpeg *mpeg = nv31_mpeg(engine);
|
||||
struct nvkm_subdev *subdev = &mpeg->engine.subdev;
|
||||
struct nvkm_device *device = subdev->device;
|
||||
u32 stat = nvkm_rd32(device, 0x00b100);
|
||||
u32 type = nvkm_rd32(device, 0x00b230);
|
||||
u32 mthd = nvkm_rd32(device, 0x00b234);
|
||||
@ -188,7 +188,7 @@ nv31_mpeg_intr(struct nvkm_subdev *subdev)
|
||||
u32 show = stat;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&mpeg->base.engine.lock, flags);
|
||||
spin_lock_irqsave(&mpeg->engine.lock, flags);
|
||||
|
||||
if (stat & 0x01000000) {
|
||||
/* happens on initial binding of the object */
|
||||
@ -213,61 +213,19 @@ nv31_mpeg_intr(struct nvkm_subdev *subdev)
|
||||
"unknown", stat, type, mthd, data);
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&mpeg->base.engine.lock, flags);
|
||||
}
|
||||
|
||||
static const struct nvkm_engine_func
|
||||
nv31_mpeg = {
|
||||
.fifo.cclass = nv31_mpeg_chan_new,
|
||||
.sclass = {
|
||||
{ -1, -1, NV31_MPEG, &nv31_mpeg_object },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
static int
|
||||
nv31_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
||||
struct nvkm_oclass *oclass, void *data, u32 size,
|
||||
struct nvkm_object **pobject)
|
||||
{
|
||||
struct nv31_mpeg *mpeg;
|
||||
int ret;
|
||||
|
||||
ret = nvkm_mpeg_create(parent, engine, oclass, &mpeg);
|
||||
*pobject = nv_object(mpeg);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
mpeg->base.engine.func = &nv31_mpeg;
|
||||
|
||||
mpeg->mthd_dma = nv31_mpeg_mthd_dma;
|
||||
nv_subdev(mpeg)->unit = 0x00000002;
|
||||
nv_subdev(mpeg)->intr = nv31_mpeg_intr;
|
||||
nv_engine(mpeg)->tile_prog = nv31_mpeg_tile_prog;
|
||||
return 0;
|
||||
spin_unlock_irqrestore(&mpeg->engine.lock, flags);
|
||||
}
|
||||
|
||||
int
|
||||
nv31_mpeg_init(struct nvkm_object *object)
|
||||
nv31_mpeg_init(struct nvkm_engine *mpeg)
|
||||
{
|
||||
struct nvkm_engine *engine = nv_engine(object);
|
||||
struct nv31_mpeg *mpeg = (void *)object;
|
||||
struct nvkm_subdev *subdev = &mpeg->base.engine.subdev;
|
||||
struct nvkm_subdev *subdev = &mpeg->subdev;
|
||||
struct nvkm_device *device = subdev->device;
|
||||
struct nvkm_fb *fb = device->fb;
|
||||
int ret, i;
|
||||
|
||||
ret = nvkm_mpeg_init(&mpeg->base);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* VPE init */
|
||||
nvkm_wr32(device, 0x00b0e0, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */
|
||||
nvkm_wr32(device, 0x00b0e8, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */
|
||||
|
||||
for (i = 0; i < fb->tile.regions; i++)
|
||||
engine->tile_prog(engine, i);
|
||||
|
||||
/* PMPEG init */
|
||||
nvkm_wr32(device, 0x00b32c, 0x00000000);
|
||||
nvkm_wr32(device, 0x00b314, 0x00000100);
|
||||
@ -290,13 +248,47 @@ nv31_mpeg_init(struct nvkm_object *object)
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct nvkm_oclass
|
||||
nv31_mpeg_oclass = {
|
||||
.handle = NV_ENGINE(MPEG, 0x31),
|
||||
.ofuncs = &(struct nvkm_ofuncs) {
|
||||
.ctor = nv31_mpeg_ctor,
|
||||
.dtor = _nvkm_mpeg_dtor,
|
||||
.init = nv31_mpeg_init,
|
||||
.fini = _nvkm_mpeg_fini,
|
||||
},
|
||||
static void *
|
||||
nv31_mpeg_dtor(struct nvkm_engine *engine)
|
||||
{
|
||||
return nv31_mpeg(engine);
|
||||
}
|
||||
|
||||
static const struct nvkm_engine_func
|
||||
nv31_mpeg_ = {
|
||||
.dtor = nv31_mpeg_dtor,
|
||||
.init = nv31_mpeg_init,
|
||||
.intr = nv31_mpeg_intr,
|
||||
.tile = nv31_mpeg_tile,
|
||||
.fifo.cclass = nv31_mpeg_chan_new,
|
||||
.sclass = {
|
||||
{ -1, -1, NV31_MPEG, &nv31_mpeg_object },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
int
|
||||
nv31_mpeg_new_(const struct nv31_mpeg_func *func, struct nvkm_device *device,
|
||||
int index, struct nvkm_engine **pmpeg)
|
||||
{
|
||||
struct nv31_mpeg *mpeg;
|
||||
|
||||
if (!(mpeg = kzalloc(sizeof(*mpeg), GFP_KERNEL)))
|
||||
return -ENOMEM;
|
||||
mpeg->func = func;
|
||||
*pmpeg = &mpeg->engine;
|
||||
|
||||
return nvkm_engine_ctor(&nv31_mpeg_, device, index, 0x00000002,
|
||||
true, &mpeg->engine);
|
||||
}
|
||||
|
||||
static const struct nv31_mpeg_func
|
||||
nv31_mpeg = {
|
||||
.mthd_dma = nv31_mpeg_mthd_dma,
|
||||
};
|
||||
|
||||
int
|
||||
nv31_mpeg_new(struct nvkm_device *device, int index, struct nvkm_engine **pmpeg)
|
||||
{
|
||||
return nv31_mpeg_new_(&nv31_mpeg, device, index, pmpeg);
|
||||
}
|
||||
|
@ -1,12 +1,19 @@
|
||||
#ifndef __NV31_MPEG_H__
|
||||
#define __NV31_MPEG_H__
|
||||
#define nv31_mpeg(p) container_of((p), struct nv31_mpeg, base.engine)
|
||||
#define nv31_mpeg(p) container_of((p), struct nv31_mpeg, engine)
|
||||
#include "priv.h"
|
||||
#include <engine/mpeg.h>
|
||||
|
||||
struct nv31_mpeg {
|
||||
struct nvkm_mpeg base;
|
||||
const struct nv31_mpeg_func *func;
|
||||
struct nvkm_engine engine;
|
||||
struct nv31_mpeg_chan *chan;
|
||||
};
|
||||
|
||||
int nv31_mpeg_new_(const struct nv31_mpeg_func *, struct nvkm_device *,
|
||||
int index, struct nvkm_engine **);
|
||||
|
||||
struct nv31_mpeg_func {
|
||||
bool (*mthd_dma)(struct nvkm_device *, u32 mthd, u32 data);
|
||||
};
|
||||
|
||||
|
@ -65,60 +65,13 @@ nv40_mpeg_mthd_dma(struct nvkm_device *device, u32 mthd, u32 data)
|
||||
return true;
|
||||
}
|
||||
|
||||
static void
|
||||
nv40_mpeg_intr(struct nvkm_subdev *subdev)
|
||||
{
|
||||
struct nv31_mpeg *mpeg = (void *)subdev;
|
||||
struct nvkm_device *device = mpeg->base.engine.subdev.device;
|
||||
u32 stat;
|
||||
|
||||
if ((stat = nvkm_rd32(device, 0x00b100)))
|
||||
nv31_mpeg_intr(subdev);
|
||||
|
||||
if ((stat = nvkm_rd32(device, 0x00b800))) {
|
||||
nvkm_error(subdev, "PMSRCH %08x\n", stat);
|
||||
nvkm_wr32(device, 0x00b800, stat);
|
||||
}
|
||||
}
|
||||
|
||||
static const struct nvkm_engine_func
|
||||
static const struct nv31_mpeg_func
|
||||
nv40_mpeg = {
|
||||
.fifo.cclass = nv31_mpeg_chan_new,
|
||||
.sclass = {
|
||||
{ -1, -1, NV31_MPEG, &nv31_mpeg_object },
|
||||
{}
|
||||
}
|
||||
.mthd_dma = nv40_mpeg_mthd_dma,
|
||||
};
|
||||
|
||||
static int
|
||||
nv40_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
||||
struct nvkm_oclass *oclass, void *data, u32 size,
|
||||
struct nvkm_object **pobject)
|
||||
int
|
||||
nv40_mpeg_new(struct nvkm_device *device, int index, struct nvkm_engine **pmpeg)
|
||||
{
|
||||
struct nv31_mpeg *mpeg;
|
||||
int ret;
|
||||
|
||||
ret = nvkm_mpeg_create(parent, engine, oclass, &mpeg);
|
||||
*pobject = nv_object(mpeg);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
mpeg->base.engine.func = &nv40_mpeg;
|
||||
|
||||
mpeg->mthd_dma = nv40_mpeg_mthd_dma;
|
||||
nv_subdev(mpeg)->unit = 0x00000002;
|
||||
nv_subdev(mpeg)->intr = nv40_mpeg_intr;
|
||||
nv_engine(mpeg)->tile_prog = nv31_mpeg_tile_prog;
|
||||
return 0;
|
||||
return nv31_mpeg_new_(&nv40_mpeg, device, index, pmpeg);
|
||||
}
|
||||
|
||||
struct nvkm_oclass
|
||||
nv40_mpeg_oclass = {
|
||||
.handle = NV_ENGINE(MPEG, 0x40),
|
||||
.ofuncs = &(struct nvkm_ofuncs) {
|
||||
.ctor = nv40_mpeg_ctor,
|
||||
.dtor = _nvkm_mpeg_dtor,
|
||||
.init = nv31_mpeg_init,
|
||||
.fini = _nvkm_mpeg_fini,
|
||||
},
|
||||
};
|
||||
|
@ -21,7 +21,7 @@
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#define nv44_mpeg(p) container_of((p), struct nv44_mpeg, base.engine)
|
||||
#define nv44_mpeg(p) container_of((p), struct nv44_mpeg, engine)
|
||||
#include "priv.h"
|
||||
|
||||
#include <core/client.h>
|
||||
@ -31,12 +31,10 @@
|
||||
#include <nvif/class.h>
|
||||
|
||||
struct nv44_mpeg {
|
||||
struct nvkm_mpeg base;
|
||||
struct nvkm_engine engine;
|
||||
struct list_head chan;
|
||||
};
|
||||
|
||||
bool nv40_mpeg_mthd_dma(struct nvkm_device *, u32, u32);
|
||||
|
||||
/*******************************************************************************
|
||||
* PMPEG context
|
||||
******************************************************************************/
|
||||
@ -72,7 +70,7 @@ nv44_mpeg_chan_fini(struct nvkm_object *object, bool suspend)
|
||||
|
||||
struct nv44_mpeg_chan *chan = nv44_mpeg_chan(object);
|
||||
struct nv44_mpeg *mpeg = chan->mpeg;
|
||||
struct nvkm_device *device = mpeg->base.engine.subdev.device;
|
||||
struct nvkm_device *device = mpeg->engine.subdev.device;
|
||||
u32 inst = 0x80000000 | (chan->inst >> 4);
|
||||
|
||||
nvkm_mask(device, 0x00b32c, 0x00000001, 0x00000000);
|
||||
@ -88,9 +86,9 @@ nv44_mpeg_chan_dtor(struct nvkm_object *object)
|
||||
struct nv44_mpeg_chan *chan = nv44_mpeg_chan(object);
|
||||
struct nv44_mpeg *mpeg = chan->mpeg;
|
||||
unsigned long flags;
|
||||
spin_lock_irqsave(&mpeg->base.engine.lock, flags);
|
||||
spin_lock_irqsave(&mpeg->engine.lock, flags);
|
||||
list_del(&chan->head);
|
||||
spin_unlock_irqrestore(&mpeg->base.engine.lock, flags);
|
||||
spin_unlock_irqrestore(&mpeg->engine.lock, flags);
|
||||
return chan;
|
||||
}
|
||||
|
||||
@ -117,9 +115,9 @@ nv44_mpeg_chan_new(struct nvkm_fifo_chan *fifoch,
|
||||
chan->fifo = fifoch;
|
||||
*pobject = &chan->object;
|
||||
|
||||
spin_lock_irqsave(&mpeg->base.engine.lock, flags);
|
||||
spin_lock_irqsave(&mpeg->engine.lock, flags);
|
||||
list_add(&chan->head, &mpeg->chan);
|
||||
spin_unlock_irqrestore(&mpeg->base.engine.lock, flags);
|
||||
spin_unlock_irqrestore(&mpeg->engine.lock, flags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -142,11 +140,12 @@ nv44_mpeg_mthd(struct nvkm_device *device, u32 mthd, u32 data)
|
||||
}
|
||||
|
||||
static void
|
||||
nv44_mpeg_intr(struct nvkm_subdev *subdev)
|
||||
nv44_mpeg_intr(struct nvkm_engine *engine)
|
||||
{
|
||||
struct nv44_mpeg *mpeg = (void *)subdev;
|
||||
struct nv44_mpeg *mpeg = nv44_mpeg(engine);
|
||||
struct nvkm_subdev *subdev = &mpeg->engine.subdev;
|
||||
struct nvkm_device *device = subdev->device;
|
||||
struct nv44_mpeg_chan *temp, *chan = NULL;
|
||||
struct nvkm_device *device = mpeg->base.engine.subdev.device;
|
||||
unsigned long flags;
|
||||
u32 inst = nvkm_rd32(device, 0x00b318) & 0x000fffff;
|
||||
u32 stat = nvkm_rd32(device, 0x00b100);
|
||||
@ -155,7 +154,7 @@ nv44_mpeg_intr(struct nvkm_subdev *subdev)
|
||||
u32 data = nvkm_rd32(device, 0x00b238);
|
||||
u32 show = stat;
|
||||
|
||||
spin_lock_irqsave(&mpeg->base.engine.lock, flags);
|
||||
spin_lock_irqsave(&mpeg->engine.lock, flags);
|
||||
list_for_each_entry(temp, &mpeg->chan, head) {
|
||||
if (temp->inst >> 4 == inst) {
|
||||
chan = temp;
|
||||
@ -188,27 +187,14 @@ nv44_mpeg_intr(struct nvkm_subdev *subdev)
|
||||
stat, type, mthd, data);
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&mpeg->base.engine.lock, flags);
|
||||
}
|
||||
|
||||
static void
|
||||
nv44_mpeg_me_intr(struct nvkm_subdev *subdev)
|
||||
{
|
||||
struct nvkm_mpeg *mpeg = (void *)subdev;
|
||||
struct nvkm_device *device = mpeg->engine.subdev.device;
|
||||
u32 stat;
|
||||
|
||||
if ((stat = nvkm_rd32(device, 0x00b100)))
|
||||
nv44_mpeg_intr(subdev);
|
||||
|
||||
if ((stat = nvkm_rd32(device, 0x00b800))) {
|
||||
nvkm_error(subdev, "PMSRCH %08x\n", stat);
|
||||
nvkm_wr32(device, 0x00b800, stat);
|
||||
}
|
||||
spin_unlock_irqrestore(&mpeg->engine.lock, flags);
|
||||
}
|
||||
|
||||
static const struct nvkm_engine_func
|
||||
nv44_mpeg = {
|
||||
.init = nv31_mpeg_init,
|
||||
.intr = nv44_mpeg_intr,
|
||||
.tile = nv31_mpeg_tile,
|
||||
.fifo.cclass = nv44_mpeg_chan_new,
|
||||
.sclass = {
|
||||
{ -1, -1, NV31_MPEG, &nv31_mpeg_object },
|
||||
@ -216,35 +202,16 @@ nv44_mpeg = {
|
||||
}
|
||||
};
|
||||
|
||||
static int
|
||||
nv44_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
||||
struct nvkm_oclass *oclass, void *data, u32 size,
|
||||
struct nvkm_object **pobject)
|
||||
int
|
||||
nv44_mpeg_new(struct nvkm_device *device, int index, struct nvkm_engine **pmpeg)
|
||||
{
|
||||
struct nv44_mpeg *mpeg;
|
||||
int ret;
|
||||
|
||||
ret = nvkm_mpeg_create(parent, engine, oclass, &mpeg);
|
||||
*pobject = nv_object(mpeg);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (!(mpeg = kzalloc(sizeof(*mpeg), GFP_KERNEL)))
|
||||
return -ENOMEM;
|
||||
INIT_LIST_HEAD(&mpeg->chan);
|
||||
mpeg->base.engine.func = &nv44_mpeg;
|
||||
*pmpeg = &mpeg->engine;
|
||||
|
||||
nv_subdev(mpeg)->unit = 0x00000002;
|
||||
nv_subdev(mpeg)->intr = nv44_mpeg_me_intr;
|
||||
nv_engine(mpeg)->tile_prog = nv31_mpeg_tile_prog;
|
||||
return 0;
|
||||
return nvkm_engine_ctor(&nv44_mpeg, device, index, 0x00000002,
|
||||
true, &mpeg->engine);
|
||||
}
|
||||
|
||||
struct nvkm_oclass
|
||||
nv44_mpeg_oclass = {
|
||||
.handle = NV_ENGINE(MPEG, 0x44),
|
||||
.ofuncs = &(struct nvkm_ofuncs) {
|
||||
.ctor = nv44_mpeg_ctor,
|
||||
.dtor = _nvkm_mpeg_dtor,
|
||||
.init = nv31_mpeg_init,
|
||||
.fini = _nvkm_mpeg_fini,
|
||||
},
|
||||
};
|
||||
|
@ -57,10 +57,10 @@ nv50_mpeg_cclass = {
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
nv50_mpeg_intr(struct nvkm_subdev *subdev)
|
||||
nv50_mpeg_intr(struct nvkm_engine *mpeg)
|
||||
{
|
||||
struct nvkm_mpeg *mpeg = (void *)subdev;
|
||||
struct nvkm_device *device = mpeg->engine.subdev.device;
|
||||
struct nvkm_subdev *subdev = &mpeg->subdev;
|
||||
struct nvkm_device *device = subdev->device;
|
||||
u32 stat = nvkm_rd32(device, 0x00b100);
|
||||
u32 type = nvkm_rd32(device, 0x00b230);
|
||||
u32 mthd = nvkm_rd32(device, 0x00b234);
|
||||
@ -84,61 +84,11 @@ nv50_mpeg_intr(struct nvkm_subdev *subdev)
|
||||
nvkm_wr32(device, 0x00b230, 0x00000001);
|
||||
}
|
||||
|
||||
static void
|
||||
nv50_vpe_intr(struct nvkm_subdev *subdev)
|
||||
{
|
||||
struct nvkm_device *device = subdev->device;
|
||||
|
||||
if (nvkm_rd32(device, 0x00b100))
|
||||
nv50_mpeg_intr(subdev);
|
||||
|
||||
if (nvkm_rd32(device, 0x00b800)) {
|
||||
u32 stat = nvkm_rd32(device, 0x00b800);
|
||||
nvkm_info(subdev, "PMSRCH: %08x\n", stat);
|
||||
nvkm_wr32(device, 0xb800, stat);
|
||||
}
|
||||
}
|
||||
|
||||
static const struct nvkm_engine_func
|
||||
nv50_mpeg = {
|
||||
.cclass = &nv50_mpeg_cclass,
|
||||
.sclass = {
|
||||
{ -1, -1, NV31_MPEG, &nv31_mpeg_object },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
static int
|
||||
nv50_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
||||
struct nvkm_oclass *oclass, void *data, u32 size,
|
||||
struct nvkm_object **pobject)
|
||||
{
|
||||
struct nvkm_mpeg *mpeg;
|
||||
int ret;
|
||||
|
||||
ret = nvkm_mpeg_create(parent, engine, oclass, &mpeg);
|
||||
*pobject = nv_object(mpeg);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
mpeg->engine.func = &nv50_mpeg;
|
||||
|
||||
nv_subdev(mpeg)->unit = 0x00400002;
|
||||
nv_subdev(mpeg)->intr = nv50_vpe_intr;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
nv50_mpeg_init(struct nvkm_object *object)
|
||||
nv50_mpeg_init(struct nvkm_engine *mpeg)
|
||||
{
|
||||
struct nvkm_mpeg *mpeg = (void *)object;
|
||||
struct nvkm_subdev *subdev = &mpeg->engine.subdev;
|
||||
struct nvkm_subdev *subdev = &mpeg->subdev;
|
||||
struct nvkm_device *device = subdev->device;
|
||||
int ret;
|
||||
|
||||
ret = nvkm_mpeg_init(mpeg);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
nvkm_wr32(device, 0x00b32c, 0x00000000);
|
||||
nvkm_wr32(device, 0x00b314, 0x00000100);
|
||||
@ -166,13 +116,20 @@ nv50_mpeg_init(struct nvkm_object *object)
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct nvkm_oclass
|
||||
nv50_mpeg_oclass = {
|
||||
.handle = NV_ENGINE(MPEG, 0x50),
|
||||
.ofuncs = &(struct nvkm_ofuncs) {
|
||||
.ctor = nv50_mpeg_ctor,
|
||||
.dtor = _nvkm_mpeg_dtor,
|
||||
.init = nv50_mpeg_init,
|
||||
.fini = _nvkm_mpeg_fini,
|
||||
},
|
||||
static const struct nvkm_engine_func
|
||||
nv50_mpeg = {
|
||||
.init = nv50_mpeg_init,
|
||||
.intr = nv50_mpeg_intr,
|
||||
.cclass = &nv50_mpeg_cclass,
|
||||
.sclass = {
|
||||
{ -1, -1, NV31_MPEG, &nv31_mpeg_object },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
int
|
||||
nv50_mpeg_new(struct nvkm_device *device, int index, struct nvkm_engine **pmpeg)
|
||||
{
|
||||
return nvkm_engine_new_(&nv50_mpeg, device, index, 0x00400002,
|
||||
true, pmpeg);
|
||||
}
|
||||
|
@ -3,7 +3,14 @@
|
||||
#include <engine/mpeg.h>
|
||||
struct nvkm_fifo_chan;
|
||||
|
||||
int nv31_mpeg_init(struct nvkm_engine *);
|
||||
void nv31_mpeg_tile(struct nvkm_engine *, int, struct nvkm_fb_tile *);
|
||||
extern const struct nvkm_object_func nv31_mpeg_object;
|
||||
|
||||
bool nv40_mpeg_mthd_dma(struct nvkm_device *, u32, u32);
|
||||
|
||||
int nv50_mpeg_init(struct nvkm_engine *);
|
||||
void nv50_mpeg_intr(struct nvkm_engine *);
|
||||
|
||||
extern const struct nvkm_object_func nv50_mpeg_cclass;
|
||||
#endif
|
||||
|
@ -56,8 +56,8 @@ nvkm_fb_tile_prog(struct nvkm_fb *fb, int region, struct nvkm_fb_tile *tile)
|
||||
fb->func->tile.prog(fb, region, tile);
|
||||
if (device->gr)
|
||||
nvkm_engine_tile(&device->gr->engine, region);
|
||||
if (likely(device->mpeg))
|
||||
device->mpeg->tile_prog(device->mpeg, region);
|
||||
if (device->mpeg)
|
||||
nvkm_engine_tile(device->mpeg, region);
|
||||
}
|
||||
}
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user