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ARM: imx6q: add usbphy clocks
Signed-off-by: Richard Zhao <richard.zhao@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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@ -152,7 +152,7 @@ enum mx6q_clks {
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ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
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usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
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pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, ssi1_ipg,
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ssi2_ipg, ssi3_ipg, rom,
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ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2,
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clk_max
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};
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@ -198,6 +198,9 @@ int __init mx6q_clocks_init(void)
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clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x2000, 0x3);
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clk[pll8_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll8_enet", "osc", base + 0xe0, 0x182000, 0x3);
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clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 6);
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clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 6);
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/* name parent_name reg idx */
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clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
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clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
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@ -405,6 +408,8 @@ int __init mx6q_clocks_init(void)
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clk_register_clkdev(clk[usboh3], NULL, "2184200.usb");
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clk_register_clkdev(clk[usboh3], NULL, "2184400.usb");
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clk_register_clkdev(clk[usboh3], NULL, "2184600.usb");
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clk_register_clkdev(clk[usbphy1], NULL, "20c9000.usbphy");
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clk_register_clkdev(clk[usbphy2], NULL, "20ca000.usbphy");
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clk_register_clkdev(clk[uart_serial], "per", "2020000.serial");
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clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial");
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clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial");
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