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soc: sifive: ccache: fix missing free_irq() in error path in sifive_ccache_init()
Add missing free_irq() before return error from sifive_ccache_init().
Fixes: a967a289f1
("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
parent
73e770f085
commit
756344e7cb
@ -240,7 +240,7 @@ static int __init sifive_ccache_init(void)
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NULL);
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if (rc) {
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pr_err("Could not request IRQ %d\n", g_irq[i]);
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goto err_unmap;
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goto err_free_irq;
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}
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}
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@ -254,6 +254,9 @@ static int __init sifive_ccache_init(void)
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#endif
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return 0;
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err_free_irq:
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while (--i >= 0)
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free_irq(g_irq[i], NULL);
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err_unmap:
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iounmap(ccache_base);
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return rc;
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