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ASoC: SOF: Intel: Add Intel specific HDA DSP HW operations
Add support for various PM and core reset/run state transitions. Signed-off-by: Keyon Jie <yang.jie@linux.intel.com> Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Reviewed-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Liam Girdwood
Mark Brown
parent
8a300c8fb1
commit
747503b181
455
sound/soc/sof/intel/hda-dsp.c
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455
sound/soc/sof/intel/hda-dsp.c
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@ -0,0 +1,455 @@
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// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
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//
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// This file is provided under a dual BSD/GPLv2 license. When using or
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// redistributing this file, you may do so under either license.
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//
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// Copyright(c) 2018 Intel Corporation. All rights reserved.
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//
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// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
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// Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
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// Rander Wang <rander.wang@intel.com>
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// Keyon Jie <yang.jie@linux.intel.com>
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//
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/*
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* Hardware interface for generic Intel audio DSP HDA IP
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*/
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#include <sound/hdaudio_ext.h>
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#include <sound/hda_register.h>
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#include "../ops.h"
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#include "hda.h"
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/*
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* DSP Core control.
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*/
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int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev, unsigned int core_mask)
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{
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u32 adspcs;
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u32 reset;
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int ret;
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/* set reset bits for cores */
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reset = HDA_DSP_ADSPCS_CRST_MASK(core_mask);
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snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_ADSPCS,
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reset, reset),
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/* poll with timeout to check if operation successful */
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ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_ADSPCS, adspcs,
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((adspcs & reset) == reset),
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HDA_DSP_REG_POLL_INTERVAL_US,
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HDA_DSP_RESET_TIMEOUT_US);
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/* has core entered reset ? */
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adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_ADSPCS);
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if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) !=
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HDA_DSP_ADSPCS_CRST_MASK(core_mask)) {
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dev_err(sdev->dev,
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"error: reset enter failed: core_mask %x adspcs 0x%x\n",
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core_mask, adspcs);
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ret = -EIO;
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}
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return ret;
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}
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int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev, unsigned int core_mask)
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{
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unsigned int crst;
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u32 adspcs;
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int ret;
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/* clear reset bits for cores */
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snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_ADSPCS,
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HDA_DSP_ADSPCS_CRST_MASK(core_mask),
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0);
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/* poll with timeout to check if operation successful */
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crst = HDA_DSP_ADSPCS_CRST_MASK(core_mask);
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ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_ADSPCS, adspcs,
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!(adspcs & crst),
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HDA_DSP_REG_POLL_INTERVAL_US,
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HDA_DSP_RESET_TIMEOUT_US);
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/* has core left reset ? */
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adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_ADSPCS);
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if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) != 0) {
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dev_err(sdev->dev,
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"error: reset leave failed: core_mask %x adspcs 0x%x\n",
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core_mask, adspcs);
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ret = -EIO;
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}
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return ret;
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}
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int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask)
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{
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/* stall core */
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snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_ADSPCS,
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HDA_DSP_ADSPCS_CSTALL_MASK(core_mask),
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HDA_DSP_ADSPCS_CSTALL_MASK(core_mask));
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/* set reset state */
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return hda_dsp_core_reset_enter(sdev, core_mask);
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}
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int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask)
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{
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int ret;
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/* leave reset state */
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ret = hda_dsp_core_reset_leave(sdev, core_mask);
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if (ret < 0)
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return ret;
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/* run core */
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dev_dbg(sdev->dev, "unstall/run core: core_mask = %x\n", core_mask);
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snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_ADSPCS,
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HDA_DSP_ADSPCS_CSTALL_MASK(core_mask),
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0);
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/* is core now running ? */
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if (!hda_dsp_core_is_enabled(sdev, core_mask)) {
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hda_dsp_core_stall_reset(sdev, core_mask);
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dev_err(sdev->dev, "error: DSP start core failed: core_mask %x\n",
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core_mask);
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ret = -EIO;
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}
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return ret;
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}
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/*
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* Power Management.
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*/
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int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask)
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{
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unsigned int cpa;
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u32 adspcs;
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int ret;
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/* update bits */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS,
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HDA_DSP_ADSPCS_SPA_MASK(core_mask),
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HDA_DSP_ADSPCS_SPA_MASK(core_mask));
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/* poll with timeout to check if operation successful */
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cpa = HDA_DSP_ADSPCS_CPA_MASK(core_mask);
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ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_ADSPCS, adspcs,
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(adspcs & cpa) == cpa,
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HDA_DSP_REG_POLL_INTERVAL_US,
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HDA_DSP_RESET_TIMEOUT_US);
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if (ret < 0)
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dev_err(sdev->dev, "error: timeout on core powerup\n");
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/* did core power up ? */
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adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_ADSPCS);
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if ((adspcs & HDA_DSP_ADSPCS_CPA_MASK(core_mask)) !=
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HDA_DSP_ADSPCS_CPA_MASK(core_mask)) {
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dev_err(sdev->dev,
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"error: power up core failed core_mask %xadspcs 0x%x\n",
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core_mask, adspcs);
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ret = -EIO;
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}
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return ret;
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}
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int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask)
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{
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u32 adspcs;
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/* update bits */
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snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_ADSPCS,
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HDA_DSP_ADSPCS_SPA_MASK(core_mask), 0);
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return snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_ADSPCS, adspcs,
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!(adspcs & HDA_DSP_ADSPCS_SPA_MASK(core_mask)),
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HDA_DSP_REG_POLL_INTERVAL_US,
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HDA_DSP_PD_TIMEOUT * USEC_PER_MSEC);
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}
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bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev,
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unsigned int core_mask)
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{
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int val;
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bool is_enable;
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val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS);
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is_enable = ((val & HDA_DSP_ADSPCS_CPA_MASK(core_mask)) &&
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(val & HDA_DSP_ADSPCS_SPA_MASK(core_mask)) &&
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!(val & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) &&
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!(val & HDA_DSP_ADSPCS_CSTALL_MASK(core_mask)));
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dev_dbg(sdev->dev, "DSP core(s) enabled? %d : core_mask %x\n",
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is_enable, core_mask);
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return is_enable;
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}
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int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask)
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{
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int ret;
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/* return if core is already enabled */
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if (hda_dsp_core_is_enabled(sdev, core_mask))
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return 0;
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/* power up */
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ret = hda_dsp_core_power_up(sdev, core_mask);
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if (ret < 0) {
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dev_err(sdev->dev, "error: dsp core power up failed: core_mask %x\n",
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core_mask);
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return ret;
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}
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return hda_dsp_core_run(sdev, core_mask);
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}
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int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
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unsigned int core_mask)
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{
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int ret;
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/* place core in reset prior to power down */
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ret = hda_dsp_core_stall_reset(sdev, core_mask);
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if (ret < 0) {
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dev_err(sdev->dev, "error: dsp core reset failed: core_mask %x\n",
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core_mask);
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return ret;
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}
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/* power down core */
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ret = hda_dsp_core_power_down(sdev, core_mask);
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if (ret < 0) {
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dev_err(sdev->dev, "error: dsp core power down fail mask %x: %d\n",
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core_mask, ret);
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return ret;
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}
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/* make sure we are in OFF state */
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if (hda_dsp_core_is_enabled(sdev, core_mask)) {
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dev_err(sdev->dev, "error: dsp core disable fail mask %x: %d\n",
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core_mask, ret);
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ret = -EIO;
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}
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return ret;
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}
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void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev)
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{
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struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
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const struct sof_intel_dsp_desc *chip = hda->desc;
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/* enable IPC DONE and BUSY interrupts */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
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HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY,
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HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY);
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/* enable IPC interrupt */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
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HDA_DSP_ADSPIC_IPC, HDA_DSP_ADSPIC_IPC);
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}
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void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev)
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{
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struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
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const struct sof_intel_dsp_desc *chip = hda->desc;
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/* disable IPC interrupt */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
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HDA_DSP_ADSPIC_IPC, 0);
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/* disable IPC BUSY and DONE interrupt */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
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HDA_DSP_REG_HIPCCTL_BUSY | HDA_DSP_REG_HIPCCTL_DONE, 0);
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}
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static int hda_suspend(struct snd_sof_dev *sdev, int state)
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{
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struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
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const struct sof_intel_dsp_desc *chip = hda->desc;
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#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
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struct hdac_bus *bus = sof_to_bus(sdev);
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#endif
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int ret;
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/* disable IPC interrupts */
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hda_dsp_ipc_int_disable(sdev);
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#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
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/* power down all hda link */
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snd_hdac_ext_bus_link_power_down_all(bus);
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#endif
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/* power down DSP */
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ret = hda_dsp_core_reset_power_down(sdev, chip->cores_mask);
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if (ret < 0) {
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dev_err(sdev->dev,
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"error: failed to power down core during suspend\n");
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return ret;
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}
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#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
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/* disable ppcap interrupt */
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snd_hdac_ext_bus_ppcap_int_enable(bus, false);
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snd_hdac_ext_bus_ppcap_enable(bus, false);
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/* disable hda bus irq and i/o */
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snd_hdac_bus_stop_chip(bus);
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#else
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/* disable ppcap interrupt */
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hda_dsp_ctrl_ppcap_enable(sdev, false);
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hda_dsp_ctrl_ppcap_int_enable(sdev, false);
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/* disable hda bus irq */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
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SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN,
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0);
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#endif
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/* disable LP retention mode */
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snd_sof_pci_update_bits(sdev, PCI_PGCTL,
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PCI_PGCTL_LSRMD_MASK, PCI_PGCTL_LSRMD_MASK);
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/* reset controller */
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ret = hda_dsp_ctrl_link_reset(sdev, true);
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if (ret < 0) {
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dev_err(sdev->dev,
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"error: failed to reset controller during suspend\n");
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return ret;
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}
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return 0;
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}
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static int hda_resume(struct snd_sof_dev *sdev)
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{
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#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
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struct hdac_bus *bus = sof_to_bus(sdev);
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struct hdac_ext_link *hlink = NULL;
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#endif
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int ret;
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/*
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* clear TCSEL to clear playback on some HD Audio
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* codecs. PCI TCSEL is defined in the Intel manuals.
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*/
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snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0);
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#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
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/* reset and start hda controller */
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ret = hda_dsp_ctrl_init_chip(sdev, true);
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if (ret < 0) {
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dev_err(sdev->dev,
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"error: failed to start controller after resume\n");
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return ret;
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}
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hda_dsp_ctrl_misc_clock_gating(sdev, false);
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/* Reset stream-to-link mapping */
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list_for_each_entry(hlink, &bus->hlink_list, list)
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bus->io_ops->reg_writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV);
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hda_dsp_ctrl_misc_clock_gating(sdev, true);
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/* enable ppcap interrupt */
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snd_hdac_ext_bus_ppcap_enable(bus, true);
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snd_hdac_ext_bus_ppcap_int_enable(bus, true);
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#else
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hda_dsp_ctrl_misc_clock_gating(sdev, false);
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/* reset controller */
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ret = hda_dsp_ctrl_link_reset(sdev, true);
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if (ret < 0) {
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dev_err(sdev->dev,
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"error: failed to reset controller during resume\n");
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return ret;
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}
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/* take controller out of reset */
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ret = hda_dsp_ctrl_link_reset(sdev, false);
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if (ret < 0) {
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dev_err(sdev->dev,
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"error: failed to ready controller during resume\n");
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return ret;
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}
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/* enable hda bus irq */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
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SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN,
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SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN);
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hda_dsp_ctrl_misc_clock_gating(sdev, true);
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/* enable ppcap interrupt */
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hda_dsp_ctrl_ppcap_enable(sdev, true);
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hda_dsp_ctrl_ppcap_int_enable(sdev, true);
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#endif
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#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
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/* turn off the links that were off before suspend */
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list_for_each_entry(hlink, &bus->hlink_list, list) {
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if (!hlink->ref_count)
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snd_hdac_ext_bus_link_power_down(hlink);
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}
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/* check dma status and clean up CORB/RIRB buffers */
|
||||
if (!bus->cmd_dma_state)
|
||||
snd_hdac_bus_stop_cmd_io(bus);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int hda_dsp_resume(struct snd_sof_dev *sdev)
|
||||
{
|
||||
/* init hda controller. DSP cores will be powered up during fw boot */
|
||||
return hda_resume(sdev);
|
||||
}
|
||||
|
||||
int hda_dsp_runtime_resume(struct snd_sof_dev *sdev)
|
||||
{
|
||||
/* init hda controller. DSP cores will be powered up during fw boot */
|
||||
return hda_resume(sdev);
|
||||
}
|
||||
|
||||
int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev, int state)
|
||||
{
|
||||
/* stop hda controller and power dsp off */
|
||||
return hda_suspend(sdev, state);
|
||||
}
|
||||
|
||||
int hda_dsp_suspend(struct snd_sof_dev *sdev, int state)
|
||||
{
|
||||
struct hdac_bus *bus = sof_to_bus(sdev);
|
||||
int ret;
|
||||
|
||||
/* stop hda controller and power dsp off */
|
||||
ret = hda_suspend(sdev, state);
|
||||
if (ret < 0) {
|
||||
dev_err(bus->dev, "error: suspending dsp\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user