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drm/i915/icl: Enable both DBuf slices during init

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ICL has 2 slices of DBuf, enable both the slices during display init.

Ideally we should only enable the second slice when needed in order to
save power, but while we're not there yet, adopt the simpler solution
to keep us bug-free.

v2 (from Paulo):
  - Add the TODO comment.
  - Reorganize where things are defined.
  - Fix indentation.
  - Remove unnecessary POSTING_READ() calls.
  - Improve the commit message.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180205154046.11485-5-paulo.r.zanoni@intel.com
This commit is contained in:
Mahesh Kumar 2018-02-05 13:40:44 -02:00 committed by Paulo Zanoni
parent ad186f3fd9
commit 746edf8f66
2 changed files with 34 additions and 2 deletions
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2
drivers/gpu/drm/i915/i915_reg.h
View File

@ -7164,6 +7164,8 @@ enum {
#define DISP_DATA_PARTITION_5_6 (1<<6) #define DISP_DATA_PARTITION_5_6 (1<<6)
#define DISP_IPC_ENABLE (1<<3) #define DISP_IPC_ENABLE (1<<3)
#define DBUF_CTL _MMIO(0x45008) #define DBUF_CTL _MMIO(0x45008)
#define DBUF_CTL_S1 _MMIO(0x45008)
#define DBUF_CTL_S2 _MMIO(0x44FE8)
#define DBUF_POWER_REQUEST (1<<31) #define DBUF_POWER_REQUEST (1<<31)
#define DBUF_POWER_STATE (1<<30) #define DBUF_POWER_STATE (1<<30)
#define GEN7_MSG_CTL _MMIO(0x45010) #define GEN7_MSG_CTL _MMIO(0x45010)

34
drivers/gpu/drm/i915/intel_runtime_pm.c
View File

@ -2646,6 +2646,36 @@ static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
DRM_ERROR("DBuf power disable timeout!\n"); DRM_ERROR("DBuf power disable timeout!\n");
} }
/*
* TODO: we shouldn't always enable DBUF_CTL_S2, we should only enable it when
* needed and keep it disabled as much as possible.
*/
static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
{
I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) | DBUF_POWER_REQUEST);
I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) | DBUF_POWER_REQUEST);
POSTING_READ(DBUF_CTL_S2);
udelay(10);
if (!(I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
!(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
DRM_ERROR("DBuf power enable timeout\n");
}
static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
{
I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) & ~DBUF_POWER_REQUEST);
I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) & ~DBUF_POWER_REQUEST);
POSTING_READ(DBUF_CTL_S2);
udelay(10);
if ((I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
DRM_ERROR("DBuf power disable timeout!\n");
}
static void skl_display_core_init(struct drm_i915_private *dev_priv, static void skl_display_core_init(struct drm_i915_private *dev_priv,
bool resume) bool resume)
{ {
@ -2957,7 +2987,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
icl_init_cdclk(dev_priv); icl_init_cdclk(dev_priv);
/* 6. Enable DBUF. */ /* 6. Enable DBUF. */
gen9_dbuf_enable(dev_priv); icl_dbuf_enable(dev_priv);
/* 7. Setup MBUS. */ /* 7. Setup MBUS. */
/* FIXME: MBUS code not here yet. */ /* FIXME: MBUS code not here yet. */
@ -2977,7 +3007,7 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
/* 1. Disable all display engine functions -> aready done */ /* 1. Disable all display engine functions -> aready done */
/* 2. Disable DBUF */ /* 2. Disable DBUF */
gen9_dbuf_disable(dev_priv); icl_dbuf_disable(dev_priv);
/* 3. Disable CD clock */ /* 3. Disable CD clock */
icl_uninit_cdclk(dev_priv); icl_uninit_cdclk(dev_priv);