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drm/i915: Fix cdclk bypass freq readout for tgl/bxt/glk

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On tgl/bxt/glk the cdclk bypass frequency depends on the PLL
reference clock. So let's read out the ref clock before we
try to compute the bypass clock.

Cc: Matt Roper <matthew.d.roper@intel.com>
Fixes: 71dc367e2b ("drm/i915: Consolidate bxt/cnl/icl cdclk readout")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190911133129.27466-1-ville.syrjala@linux.intel.com
This commit is contained in:
Ville Syrjälä 2019-09-11 16:31:26 +03:00 committed by Chris Wilson
parent 249778704c
commit 74689ddfb7
1 changed files with 2 additions and 1 deletions
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3
drivers/gpu/drm/i915/display/intel_cdclk.c
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@ -1351,6 +1351,8 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
u32 divider;
int div;
bxt_de_pll_readout(dev_priv, cdclk_state);
if (INTEL_GEN(dev_priv) >= 12)
cdclk_state->bypass = cdclk_state->ref / 2;
else if (INTEL_GEN(dev_priv) >= 11)
@ -1358,7 +1360,6 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
else
cdclk_state->bypass = cdclk_state->ref;
bxt_de_pll_readout(dev_priv, cdclk_state);
if (cdclk_state->vco == 0) {
cdclk_state->cdclk = cdclk_state->bypass;
goto out;