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powerpc/86xx: Board support for GE Fanuc's PPC9A
Support for the PPC9A VME Single Board Computer from GE Fanuc (PowerPC MPC8641D). This is the basic board support for GE Fanuc's PPC9A, a 6U single board computer, based on Freescale's MPC8641D. Signed-off-by: Martyn Welch <martyn.welch@gefanuc.com> Signed-off-by: Wim Van Sebroeck <wim@iguana.be> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Martyn Welch
Kumar Gala
parent
6e27cca915
commit
740d36ae63
364
arch/powerpc/boot/dts/gef_ppc9a.dts
Normal file
364
arch/powerpc/boot/dts/gef_ppc9a.dts
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@ -0,0 +1,364 @@
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/*
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* GE Fanuc PPC9A Device Tree Source
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*
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* Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* Based on: SBS CM6 Device Tree Source
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* Copyright 2007 SBS Technologies GmbH & Co. KG
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* And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
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* Copyright 2006 Freescale Semiconductor Inc.
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*/
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/*
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* Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
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*/
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/dts-v1/;
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/ {
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model = "GEF_PPC9A";
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compatible = "gef,ppc9a";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8641@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <32>; // 32 bytes
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i-cache-line-size = <32>; // 32 bytes
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d-cache-size = <32768>; // L1, 32K
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i-cache-size = <32768>; // L1, 32K
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timebase-frequency = <0>; // From uboot
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bus-frequency = <0>; // From uboot
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clock-frequency = <0>; // From uboot
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};
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PowerPC,8641@1 {
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device_type = "cpu";
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reg = <1>;
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d-cache-line-size = <32>; // 32 bytes
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i-cache-line-size = <32>; // 32 bytes
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d-cache-size = <32768>; // L1, 32K
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i-cache-size = <32768>; // L1, 32K
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timebase-frequency = <0>; // From uboot
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bus-frequency = <0>; // From uboot
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clock-frequency = <0>; // From uboot
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};
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x40000000>; // set by uboot
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};
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localbus@fef05000 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "fsl,mpc8641-localbus", "simple-bus";
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reg = <0xfef05000 0x1000>;
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interrupts = <19 2>;
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interrupt-parent = <&mpic>;
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ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
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1 0 0xe8000000 0x08000000 // Paged Flash 0
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2 0 0xe0000000 0x08000000 // Paged Flash 1
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3 0 0xfc100000 0x00020000 // NVRAM
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4 0 0xfc000000 0x00008000 // FPGA
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5 0 0xfc008000 0x00008000 // AFIX FPGA
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6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
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7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
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/* flash@0,0 is a mirror of part of the memory in flash@1,0
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flash@0,0 {
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compatible = "gef,ppc9a-firmware-mirror", "cfi-flash";
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reg = <0x0 0x0 0x1000000>;
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bank-width = <4>;
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device-width = <2>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "firmware";
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reg = <0x0 0x1000000>;
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read-only;
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};
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};
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*/
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flash@1,0 {
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compatible = "gef,ppc9a-paged-flash", "cfi-flash";
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reg = <0x1 0x0 0x8000000>;
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bank-width = <4>;
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device-width = <2>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "user";
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reg = <0x0 0x7800000>;
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};
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partition@7800000 {
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label = "firmware";
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reg = <0x7800000 0x800000>;
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read-only;
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};
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};
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fpga@4,0 {
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compatible = "gef,ppc9a-fpga-regs";
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reg = <0x4 0x0 0x40>;
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};
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wdt@4,2000 {
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compatible = "gef,ppc9a-fpga-wdt", "gef,fpga-wdt-1.00",
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"gef,fpga-wdt";
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reg = <0x4 0x2000 0x8>;
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interrupts = <0x1a 0x4>;
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interrupt-parent = <&gef_pic>;
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};
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/* Second watchdog available, driver currently supports one.
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wdt@4,2010 {
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compatible = "gef,ppc9a-fpga-wdt", "gef,fpga-wdt-1.00",
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"gef,fpga-wdt";
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reg = <0x4 0x2010 0x8>;
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interrupts = <0x1b 0x4>;
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interrupt-parent = <&gef_pic>;
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};
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*/
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gef_pic: pic@4,4000 {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "gef,ppc9a-fpga-pic", "gef,fpga-pic-1.00";
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reg = <0x4 0x4000 0x20>;
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interrupts = <0x8
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0x9>;
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interrupt-parent = <&mpic>;
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};
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gef_gpio: gpio@7,14000 {
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#gpio-cells = <2>;
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compatible = "gef,ppc9a-gpio", "gef,sbc610-gpio";
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reg = <0x7 0x14000 0x24>;
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gpio-controller;
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};
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};
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soc@fef00000 {
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#address-cells = <1>;
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#size-cells = <1>;
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#interrupt-cells = <2>;
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compatible = "fsl,mpc8641-soc", "simple-bus";
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ranges = <0x0 0xfef00000 0x00100000>;
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reg = <0xfef00000 0x100000>; // CCSRBAR 1M
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bus-frequency = <33333333>;
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i2c1: i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <0x2b 0x2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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hwmon@48 {
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compatible = "national,lm92";
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reg = <0x48>;
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};
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hwmon@4c {
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compatible = "adi,adt7461";
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reg = <0x4c>;
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};
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rtc@51 {
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compatible = "epson,rx8581";
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reg = <0x00000051>;
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};
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eti@6b {
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compatible = "dallas,ds1682";
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reg = <0x6b>;
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};
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};
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i2c2: i2c@3100 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl-i2c";
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reg = <0x3100 0x100>;
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interrupts = <0x2b 0x2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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dma@21300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
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reg = <0x21300 0x4>;
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ranges = <0x0 0x21100 0x200>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,mpc8641-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x0 0x80>;
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cell-index = <0>;
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interrupt-parent = <&mpic>;
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interrupts = <20 2>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8641-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupt-parent = <&mpic>;
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interrupts = <21 2>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8641-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupt-parent = <&mpic>;
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interrupts = <22 2>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8641-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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cell-index = <3>;
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interrupt-parent = <&mpic>;
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interrupts = <23 2>;
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};
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};
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mdio@24520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-mdio";
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reg = <0x24520 0x20>;
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phy0: ethernet-phy@0 {
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interrupt-parent = <&gef_pic>;
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interrupts = <0x9 0x4>;
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reg = <1>;
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};
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phy2: ethernet-phy@2 {
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interrupt-parent = <&gef_pic>;
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interrupts = <0x8 0x4>;
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reg = <3>;
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};
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};
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enet0: ethernet@24000 {
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x24000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy0>;
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phy-connection-type = "gmii";
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};
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enet1: ethernet@26000 {
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x26000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <0x1f 0x2 0x20 0x2 0x21 0x2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy2>;
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phy-connection-type = "gmii";
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};
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4500 0x100>;
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clock-frequency = <0>;
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interrupts = <0x2a 0x2>;
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interrupt-parent = <&mpic>;
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};
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serial1: serial@4600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4600 0x100>;
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clock-frequency = <0>;
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interrupts = <0x1c 0x2>;
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interrupt-parent = <&mpic>;
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};
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mpic: pic@40000 {
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clock-frequency = <0>;
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x40000 0x40000>;
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compatible = "chrp,open-pic";
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device_type = "open-pic";
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};
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global-utilities@e0000 {
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compatible = "fsl,mpc8641-guts";
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reg = <0xe0000 0x1000>;
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fsl,has-rstcr;
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};
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};
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pci0: pcie@fef08000 {
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compatible = "fsl,mpc8641-pcie";
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xfef08000 0x1000>;
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bus-range = <0x0 0xff>;
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ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
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0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
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clock-frequency = <33333333>;
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interrupt-parent = <&mpic>;
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interrupts = <0x18 0x2>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
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0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
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0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
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0x0000 0x0 0x0 0x4 &mpic 0x3 0x1
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>;
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pcie@0 {
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reg = <0 0 0 0 0>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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ranges = <0x02000000 0x0 0x80000000
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0x02000000 0x0 0x80000000
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0x0 0x40000000
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0x01000000 0x0 0x00000000
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0x01000000 0x0 0x00000000
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0x0 0x00400000>;
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};
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};
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};
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@ -31,6 +31,14 @@ config MPC8610_HPCD
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help
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This option enables support for the MPC8610 HPCD board.
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config GEF_PPC9A
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bool "GE Fanuc PPC9A"
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select DEFAULT_UIMAGE
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select GENERIC_GPIO
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select ARCH_REQUIRE_GPIOLIB
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help
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This option enables support for GE Fanuc's PPC9A.
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config GEF_SBC310
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bool "GE Fanuc SBC310"
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select DEFAULT_UIMAGE
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@ -56,7 +64,7 @@ config MPC8641
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select FSL_PCI if PCI
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select PPC_UDBG_16550
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select MPIC
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default y if MPC8641_HPCN || SBC8641D || GEF_SBC610 || GEF_SBC310
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default y if MPC8641_HPCN || SBC8641D || GEF_SBC610 || GEF_SBC310 || GEF_PPC9A
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config MPC8610
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bool
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@ -10,3 +10,4 @@ obj-$(CONFIG_MPC8610_HPCD) += mpc8610_hpcd.o
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gef-gpio-$(CONFIG_GPIOLIB) += gef_gpio.o
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obj-$(CONFIG_GEF_SBC610) += gef_sbc610.o gef_pic.o $(gef-gpio-y)
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obj-$(CONFIG_GEF_SBC310) += gef_sbc310.o gef_pic.o $(gef-gpio-y)
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obj-$(CONFIG_GEF_PPC9A) += gef_ppc9a.o gef_pic.o $(gef-gpio-y)
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223
arch/powerpc/platforms/86xx/gef_ppc9a.c
Normal file
223
arch/powerpc/platforms/86xx/gef_ppc9a.c
Normal file
@ -0,0 +1,223 @@
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/*
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* GE Fanuc PPC9A board support
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*
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* Author: Martyn Welch <martyn.welch@gefanuc.com>
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*
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* Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
|
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* under the terms of the GNU General Public License as published by the
|
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* Free Software Foundation; either version 2 of the License, or (at your
|
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* option) any later version.
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*
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* Based on: mpc86xx_hpcn.c (MPC86xx HPCN board specific routines)
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* Copyright 2006 Freescale Semiconductor Inc.
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*
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* NEC fixup adapted from arch/mips/pci/fixup-lm2e.c
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/delay.h>
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#include <linux/seq_file.h>
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#include <linux/of_platform.h>
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#include <asm/system.h>
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#include <asm/time.h>
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#include <asm/machdep.h>
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#include <asm/pci-bridge.h>
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#include <asm/mpc86xx.h>
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#include <asm/prom.h>
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#include <mm/mmu_decl.h>
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#include <asm/udbg.h>
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#include <asm/mpic.h>
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#include <sysdev/fsl_pci.h>
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#include <sysdev/fsl_soc.h>
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#include "mpc86xx.h"
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#include "gef_pic.h"
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#undef DEBUG
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#ifdef DEBUG
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#define DBG (fmt...) do { printk(KERN_ERR "PPC9A: " fmt); } while (0)
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#else
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#define DBG (fmt...) do { } while (0)
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#endif
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void __iomem *ppc9a_regs;
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static void __init gef_ppc9a_init_irq(void)
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{
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struct device_node *cascade_node = NULL;
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|
||||
mpc86xx_init_irq();
|
||||
|
||||
/*
|
||||
* There is a simple interrupt handler in the main FPGA, this needs
|
||||
* to be cascaded into the MPIC
|
||||
*/
|
||||
cascade_node = of_find_compatible_node(NULL, NULL, "gef,fpga-pic-1.00");
|
||||
if (!cascade_node) {
|
||||
printk(KERN_WARNING "PPC9A: No FPGA PIC\n");
|
||||
return;
|
||||
}
|
||||
|
||||
gef_pic_init(cascade_node);
|
||||
of_node_put(cascade_node);
|
||||
}
|
||||
|
||||
static void __init gef_ppc9a_setup_arch(void)
|
||||
{
|
||||
struct device_node *regs;
|
||||
#ifdef CONFIG_PCI
|
||||
struct device_node *np;
|
||||
|
||||
for_each_compatible_node(np, "pci", "fsl,mpc8641-pcie") {
|
||||
fsl_add_bridge(np, 1);
|
||||
}
|
||||
#endif
|
||||
|
||||
printk(KERN_INFO "GE Fanuc Intelligent Platforms PPC9A 6U VME SBC\n");
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
mpc86xx_smp_init();
|
||||
#endif
|
||||
|
||||
/* Remap basic board registers */
|
||||
regs = of_find_compatible_node(NULL, NULL, "gef,ppc9a-fpga-regs");
|
||||
if (regs) {
|
||||
ppc9a_regs = of_iomap(regs, 0);
|
||||
if (ppc9a_regs == NULL)
|
||||
printk(KERN_WARNING "Unable to map board registers\n");
|
||||
of_node_put(regs);
|
||||
}
|
||||
}
|
||||
|
||||
/* Return the PCB revision */
|
||||
static unsigned int gef_ppc9a_get_pcb_rev(void)
|
||||
{
|
||||
unsigned int reg;
|
||||
|
||||
reg = ioread32(ppc9a_regs);
|
||||
return (reg >> 8) & 0xff;
|
||||
}
|
||||
|
||||
/* Return the board (software) revision */
|
||||
static unsigned int gef_ppc9a_get_board_rev(void)
|
||||
{
|
||||
unsigned int reg;
|
||||
|
||||
reg = ioread32(ppc9a_regs);
|
||||
return (reg >> 16) & 0xff;
|
||||
}
|
||||
|
||||
/* Return the FPGA revision */
|
||||
static unsigned int gef_ppc9a_get_fpga_rev(void)
|
||||
{
|
||||
unsigned int reg;
|
||||
|
||||
reg = ioread32(ppc9a_regs);
|
||||
return (reg >> 24) & 0xf;
|
||||
}
|
||||
|
||||
static void gef_ppc9a_show_cpuinfo(struct seq_file *m)
|
||||
{
|
||||
uint svid = mfspr(SPRN_SVR);
|
||||
|
||||
seq_printf(m, "Vendor\t\t: GE Fanuc Intelligent Platforms\n");
|
||||
|
||||
seq_printf(m, "Revision\t: %u%c\n", gef_ppc9a_get_pcb_rev(),
|
||||
('A' + gef_ppc9a_get_board_rev() - 1));
|
||||
seq_printf(m, "FPGA Revision\t: %u\n", gef_ppc9a_get_fpga_rev());
|
||||
|
||||
seq_printf(m, "SVR\t\t: 0x%x\n", svid);
|
||||
}
|
||||
|
||||
static void __init gef_ppc9a_nec_fixup(struct pci_dev *pdev)
|
||||
{
|
||||
unsigned int val;
|
||||
|
||||
/* Do not do the fixup on other platforms! */
|
||||
if (!machine_is(gef_ppc9a))
|
||||
return;
|
||||
|
||||
printk(KERN_INFO "Running NEC uPD720101 Fixup\n");
|
||||
|
||||
/* Ensure ports 1, 2, 3, 4 & 5 are enabled */
|
||||
pci_read_config_dword(pdev, 0xe0, &val);
|
||||
pci_write_config_dword(pdev, 0xe0, (val & ~7) | 0x5);
|
||||
|
||||
/* System clock is 48-MHz Oscillator and EHCI Enabled. */
|
||||
pci_write_config_dword(pdev, 0xe4, 1 << 5);
|
||||
}
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB,
|
||||
gef_ppc9a_nec_fixup);
|
||||
|
||||
/*
|
||||
* Called very early, device-tree isn't unflattened
|
||||
*
|
||||
* This function is called to determine whether the BSP is compatible with the
|
||||
* supplied device-tree, which is assumed to be the correct one for the actual
|
||||
* board. It is expected thati, in the future, a kernel may support multiple
|
||||
* boards.
|
||||
*/
|
||||
static int __init gef_ppc9a_probe(void)
|
||||
{
|
||||
unsigned long root = of_get_flat_dt_root();
|
||||
|
||||
if (of_flat_dt_is_compatible(root, "gef,ppc9a"))
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static long __init mpc86xx_time_init(void)
|
||||
{
|
||||
unsigned int temp;
|
||||
|
||||
/* Set the time base to zero */
|
||||
mtspr(SPRN_TBWL, 0);
|
||||
mtspr(SPRN_TBWU, 0);
|
||||
|
||||
temp = mfspr(SPRN_HID0);
|
||||
temp |= HID0_TBEN;
|
||||
mtspr(SPRN_HID0, temp);
|
||||
asm volatile("isync");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static __initdata struct of_device_id of_bus_ids[] = {
|
||||
{ .compatible = "simple-bus", },
|
||||
{},
|
||||
};
|
||||
|
||||
static int __init declare_of_platform_devices(void)
|
||||
{
|
||||
printk(KERN_DEBUG "Probe platform devices\n");
|
||||
of_platform_bus_probe(NULL, of_bus_ids, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
machine_device_initcall(gef_ppc9a, declare_of_platform_devices);
|
||||
|
||||
define_machine(gef_ppc9a) {
|
||||
.name = "GE Fanuc PPC9A",
|
||||
.probe = gef_ppc9a_probe,
|
||||
.setup_arch = gef_ppc9a_setup_arch,
|
||||
.init_IRQ = gef_ppc9a_init_irq,
|
||||
.show_cpuinfo = gef_ppc9a_show_cpuinfo,
|
||||
.get_irq = mpic_get_irq,
|
||||
.restart = fsl_rstcr_restart,
|
||||
.time_init = mpc86xx_time_init,
|
||||
.calibrate_decr = generic_calibrate_decr,
|
||||
.progress = udbg_progress,
|
||||
#ifdef CONFIG_PCI
|
||||
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
|
||||
#endif
|
||||
};
|
||||
@ -772,7 +772,7 @@ config TXX9_WDT
|
||||
|
||||
config GEF_WDT
|
||||
tristate "GE Fanuc Watchdog Timer"
|
||||
depends on GEF_SBC610 || GEF_SBC310
|
||||
depends on GEF_SBC610 || GEF_SBC310 || GEF_PPC9A
|
||||
---help---
|
||||
Watchdog timer found in a number of GE Fanuc single board computers.
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user