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drm/i915/pps: abstract intel_pps_encoder_reset()

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Add an "encoder reset" call to hide some more pps functions, and clean
up the callers. A minor functional change is not holding the pps lock
across the whole operation in intel_dp_encoder_reset, but instead doing
it in two steps.

v2: rename intel_pps_reinit to intel_pps_encoder_reset for clarity

Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/84a50f2700b19c6719cd3e1e931c64f1e2027551.1610127741.git.jani.nikula@intel.com
This commit is contained in:
Jani Nikula 2021-01-08 19:44:16 +02:00
parent c520869ac4
commit 73bb78b5ba
3 changed files with 25 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
drivers/gpu/drm/i915/display/intel_dp.c
View File

@ -6350,30 +6350,20 @@ void intel_dp_encoder_reset(struct drm_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->dev);
struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
intel_wakeref_t wakeref;
if (!HAS_DDI(dev_priv))
intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
intel_dp->reset_link_params = true;
if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
!intel_dp_is_edp(intel_dp))
return;
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
intel_wakeref_t wakeref;
with_intel_pps_lock(intel_dp, wakeref) {
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
with_intel_pps_lock(intel_dp, wakeref)
intel_dp->active_pipe = vlv_active_pipe(intel_dp);
if (intel_dp_is_edp(intel_dp)) {
/*
* Reinit the power sequencer, in case BIOS did
* something nasty with it.
*/
intel_dp_pps_init(intel_dp);
intel_pps_vdd_sanitize(intel_dp);
}
}
intel_pps_encoder_reset(intel_dp);
}
static int intel_modeset_tile_group(struct intel_atomic_state *state,

21
drivers/gpu/drm/i915/display/intel_pps.c
View File

@ -1040,7 +1040,7 @@ void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
}
void intel_pps_vdd_sanitize(struct intel_dp *intel_dp)
static void intel_pps_vdd_sanitize(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@ -1337,7 +1337,7 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
(intel_de_read(dev_priv, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
}
void intel_dp_pps_init(struct intel_dp *intel_dp)
static void intel_dp_pps_init(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@ -1349,6 +1349,23 @@ void intel_dp_pps_init(struct intel_dp *intel_dp)
}
}
void intel_pps_encoder_reset(struct intel_dp *intel_dp)
{
intel_wakeref_t wakeref;
if (!intel_dp_is_edp(intel_dp))
return;
with_intel_pps_lock(intel_dp, wakeref) {
/*
* Reinit the power sequencer, in case BIOS did something nasty
* with it.
*/
intel_dp_pps_init(intel_dp);
intel_pps_vdd_sanitize(intel_dp);
}
}
void intel_pps_init(struct intel_dp *intel_dp)
{
intel_wakeref_t wakeref;

3
drivers/gpu/drm/i915/display/intel_pps.h
View File

@ -32,7 +32,6 @@ void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync);
void intel_pps_on_unlocked(struct intel_dp *intel_dp);
void intel_pps_off_unlocked(struct intel_dp *intel_dp);
void intel_pps_vdd_sanitize(struct intel_dp *intel_dp);
void intel_pps_vdd_on(struct intel_dp *intel_dp);
void intel_pps_on(struct intel_dp *intel_dp);
void intel_pps_off(struct intel_dp *intel_dp);
@ -42,7 +41,7 @@ bool intel_pps_have_power(struct intel_dp *intel_dp);
void wait_panel_power_cycle(struct intel_dp *intel_dp);
void intel_pps_init(struct intel_dp *intel_dp);
void intel_dp_pps_init(struct intel_dp *intel_dp);
void intel_pps_encoder_reset(struct intel_dp *intel_dp);
void intel_power_sequencer_reset(struct drm_i915_private *i915);
void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,