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drm/i915/fbc: Clean up all register defines
The FBC register defines are a mess: - namespace changes between DPFC_, FBC_, and some platform specific prefix at a whim - ilk+ reuses most g4x bits but still has some separate bit defines elsewhere - it's not clear from the defines that the bit defines are shared So let's clean it up: - both g4x and ilk register share the same defines now - only defines which conflict have a _PLATFORM suffix, everyone else just gets comments to indicate which platforms do what - namespace is consistent DPFC_ now - SNB system agent fence registers also get a consistent namespace - REG_BIT() & co. for everything Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211104144520.22605-13-ville.syrjala@linux.intel.com Acked-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com>
This commit is contained in:
Ville Syrjälä
parent
a465538370
commit
73ab6ec909
@ -322,16 +322,16 @@ static u32 g4x_dpfc_ctl(struct drm_i915_private *i915)
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u32 dpfc_ctl;
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dpfc_ctl = g4x_dpfc_ctl_limit(i915) |
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DPFC_CTL_PLANE(params->crtc.i9xx_plane);
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DPFC_CTL_PLANE_G4X(params->crtc.i9xx_plane);
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if (IS_G4X(i915))
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dpfc_ctl |= DPFC_SR_EN;
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dpfc_ctl |= DPFC_CTL_SR_EN;
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if (params->fence_id >= 0) {
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dpfc_ctl |= DPFC_CTL_FENCE_EN;
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dpfc_ctl |= DPFC_CTL_FENCE_EN_G4X;
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if (DISPLAY_VER(i915) < 6)
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dpfc_ctl |= params->fence_id;
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dpfc_ctl |= DPFC_CTL_FENCENO(params->fence_id);
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}
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return dpfc_ctl;
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@ -416,7 +416,7 @@ static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
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static bool ilk_fbc_is_compressing(struct drm_i915_private *i915)
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{
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return intel_de_read(i915, ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK;
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return intel_de_read(i915, ILK_DPFC_STATUS) & DPFC_COMP_SEG_MASK;
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}
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static void ilk_fbc_program_cfb(struct drm_i915_private *i915)
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@ -441,10 +441,10 @@ static void snb_fbc_program_fence(struct drm_i915_private *i915)
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u32 ctl = 0;
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if (params->fence_id >= 0)
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ctl = SNB_CPU_FENCE_ENABLE | params->fence_id;
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ctl = SNB_DPFC_FENCE_EN | SNB_DPFC_FENCENO(params->fence_id);
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intel_de_write(i915, SNB_DPFC_CTL_SA, ctl);
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intel_de_write(i915, DPFC_CPU_FENCE_OFFSET, params->fence_y_offset);
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intel_de_write(i915, SNB_DPFC_CPU_FENCE_OFFSET, params->fence_y_offset);
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}
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static void snb_fbc_activate(struct drm_i915_private *dev_priv)
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@ -506,13 +506,13 @@ static u32 ivb_dpfc_ctl(struct drm_i915_private *i915)
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dpfc_ctl = g4x_dpfc_ctl_limit(i915);
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if (IS_IVYBRIDGE(i915))
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dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.i9xx_plane);
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dpfc_ctl |= DPFC_CTL_PLANE_IVB(params->crtc.i9xx_plane);
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if (params->fence_id >= 0)
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dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
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dpfc_ctl |= DPFC_CTL_FENCE_EN_IVB;
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if (i915->fbc.false_color)
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dpfc_ctl |= FBC_CTL_FALSE_COLOR;
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dpfc_ctl |= DPFC_CTL_FALSE_COLOR;
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return dpfc_ctl;
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}
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@ -533,14 +533,14 @@ static void ivb_fbc_activate(struct drm_i915_private *dev_priv)
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static bool ivb_fbc_is_compressing(struct drm_i915_private *i915)
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{
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return intel_de_read(i915, IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK;
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return intel_de_read(i915, ILK_DPFC_STATUS2) & DPFC_COMP_SEG_MASK_IVB;
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}
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static void ivb_fbc_set_false_color(struct drm_i915_private *i915,
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bool enable)
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{
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intel_de_rmw(i915, ILK_DPFC_CONTROL,
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FBC_CTL_FALSE_COLOR, enable ? FBC_CTL_FALSE_COLOR : 0);
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DPFC_CTL_FALSE_COLOR, enable ? DPFC_CTL_FALSE_COLOR : 0);
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}
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static const struct intel_fbc_funcs ivb_fbc_funcs = {
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@ -3343,56 +3343,55 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
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/* Framebuffer compression for GM45+ */
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#define DPFC_CB_BASE _MMIO(0x3200)
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#define DPFC_CONTROL _MMIO(0x3208)
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#define DPFC_CTL_EN (1 << 31)
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#define DPFC_CTL_PLANE(plane) ((plane) << 30)
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#define IVB_DPFC_CTL_PLANE(plane) ((plane) << 29)
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#define DPFC_CTL_FENCE_EN (1 << 29)
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#define IVB_DPFC_CTL_FENCE_EN (1 << 28)
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#define DPFC_CTL_PERSISTENT_MODE (1 << 25)
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#define DPFC_SR_EN (1 << 10)
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#define DPFC_CTL_LIMIT_1X (0 << 6)
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#define DPFC_CTL_LIMIT_2X (1 << 6)
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#define DPFC_CTL_LIMIT_4X (2 << 6)
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#define DPFC_RECOMP_CTL _MMIO(0x320c)
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#define DPFC_RECOMP_STALL_EN (1 << 27)
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#define DPFC_RECOMP_STALL_WM_SHIFT (16)
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#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
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#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
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#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
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#define DPFC_STATUS _MMIO(0x3210)
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#define DPFC_INVAL_SEG_SHIFT (16)
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#define DPFC_INVAL_SEG_MASK (0x07ff0000)
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#define DPFC_COMP_SEG_SHIFT (0)
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#define DPFC_COMP_SEG_MASK (0x000007ff)
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#define DPFC_STATUS2 _MMIO(0x3214)
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#define DPFC_FENCE_YOFF _MMIO(0x3218)
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#define DPFC_CHICKEN _MMIO(0x3224)
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#define DPFC_HT_MODIFY (1 << 31)
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/* Framebuffer compression for Ironlake */
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#define ILK_DPFC_CB_BASE _MMIO(0x43200)
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#define DPFC_CONTROL _MMIO(0x3208)
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#define ILK_DPFC_CONTROL _MMIO(0x43208)
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#define FBC_CTL_FALSE_COLOR (1 << 10)
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/* The bit 28-8 is reserved */
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#define DPFC_RESERVED (0x1FFFFF00)
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#define DPFC_CTL_EN REG_BIT(31)
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#define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */
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#define DPFC_CTL_PLANE_G4X(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane))
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#define DPFC_CTL_FENCE_EN_G4X REG_BIT(29) /* g4x-snb */
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#define DPFC_CTL_PLANE_MASK_IVB REG_GENMASK(30, 29) /* ivb only */
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#define DPFC_CTL_PLANE_IVB(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_IVB, (i9xx_plane))
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#define DPFC_CTL_FENCE_EN_IVB REG_BIT(28) /* ivb+ */
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#define DPFC_CTL_PERSISTENT_MODE REG_BIT(25) /* g4x-snb */
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#define DPFC_CTL_FALSE_COLOR REG_BIT(10) /* ivb+ */
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#define DPFC_CTL_SR_EN REG_BIT(10) /* g4x only */
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#define DPFC_CTL_SR_EXIT_DIS REG_BIT(9) /* g4x only */
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#define DPFC_CTL_LIMIT_MASK REG_GENMASK(7, 6)
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#define DPFC_CTL_LIMIT_1X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 0)
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#define DPFC_CTL_LIMIT_2X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 1)
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#define DPFC_CTL_LIMIT_4X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 2)
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#define DPFC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
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#define DPFC_CTL_FENCENO(fence) REG_FIELD_PREP(DPFC_CTL_FENCENO_MASK, (fence))
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#define DPFC_RECOMP_CTL _MMIO(0x320c)
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#define ILK_DPFC_RECOMP_CTL _MMIO(0x4320c)
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#define DPFC_RECOMP_STALL_EN REG_BIT(27)
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#define DPFC_RECOMP_STALL_WM_MASK REG_GENMASK(26, 16)
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#define DPFC_RECOMP_TIMER_COUNT_MASK REG_GENMASK(5, 0)
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#define DPFC_STATUS _MMIO(0x3210)
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#define ILK_DPFC_STATUS _MMIO(0x43210)
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#define ILK_DPFC_COMP_SEG_MASK 0x7ff
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#define IVB_FBC_STATUS2 _MMIO(0x43214)
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#define IVB_FBC_COMP_SEG_MASK 0xfff
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#define DPFC_INVAL_SEG_MASK REG_GENMASK(26, 16)
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#define DPFC_COMP_SEG_MASK REG_GENMASK(10, 0)
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#define DPFC_STATUS2 _MMIO(0x3214)
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#define ILK_DPFC_STATUS2 _MMIO(0x43214)
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#define DPFC_COMP_SEG_MASK_IVB REG_GENMASK(11, 0)
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#define DPFC_FENCE_YOFF _MMIO(0x3218)
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#define ILK_DPFC_FENCE_YOFF _MMIO(0x43218)
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#define DPFC_CHICKEN _MMIO(0x3224)
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#define ILK_DPFC_CHICKEN _MMIO(0x43224)
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#define ILK_DPFC_DISABLE_DUMMY0 (1 << 8)
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#define ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL (1 << 14)
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#define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1 << 23)
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#define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */
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#define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */
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#define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14) /* glk+ */
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#define DPFC_DISABLE_DUMMY0 REG_BIT(8) /* ivb+ */
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#define GLK_FBC_STRIDE _MMIO(0x43228)
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#define FBC_STRIDE_OVERRIDE REG_BIT(15)
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#define FBC_STRIDE_MASK REG_GENMASK(14, 0)
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#define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x))
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#define ILK_FBC_RT_BASE _MMIO(0x2128)
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#define ILK_FBC_RT_VALID (1 << 0)
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#define SNB_FBC_FRONT_BUFFER (1 << 1)
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#define ILK_FBC_RT_VALID REG_BIT(0)
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#define SNB_FBC_FRONT_BUFFER REG_BIT(1)
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#define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
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#define ILK_FBCQ_DIS (1 << 22)
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@ -3416,8 +3415,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
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* The following two registers are of type GTTMMADR
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*/
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#define SNB_DPFC_CTL_SA _MMIO(0x100100)
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#define SNB_CPU_FENCE_ENABLE (1 << 29)
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#define DPFC_CPU_FENCE_OFFSET _MMIO(0x100104)
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#define SNB_DPFC_FENCE_EN REG_BIT(29)
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#define SNB_DPFC_FENCENO_MASK REG_GENMASK(4, 0)
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#define SNB_DPFC_FENCENO(fence) REG_FIELD_PREP(SNB_DPFC_FENCENO_MASK, (fence))
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#define SNB_DPFC_CPU_FENCE_OFFSET _MMIO(0x100104)
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/* Framebuffer compression for Ivybridge */
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#define IVB_FBC_RT_BASE _MMIO(0x7020)
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@ -3427,8 +3428,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
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#define IPS_ENABLE (1 << 31)
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#define MSG_FBC_REND_STATE _MMIO(0x50380)
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#define FBC_REND_NUKE (1 << 2)
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#define FBC_REND_CACHE_CLEAN (1 << 1)
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#define FBC_REND_NUKE REG_BIT(2)
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#define FBC_REND_CACHE_CLEAN REG_BIT(1)
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/*
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* GPIO regs
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@ -161,7 +161,7 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
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* Display WA #0883: bxt
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*/
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intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
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ILK_DPFC_DISABLE_DUMMY0);
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DPFC_DISABLE_DUMMY0);
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}
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static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
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@ -7435,7 +7435,7 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
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{
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/* Wa_1409120013:icl,ehl */
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intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
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ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
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DPFC_CHICKEN_COMP_DUMMY_PIXEL);
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/*Wa_14010594013:icl, ehl */
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intel_uncore_rmw(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
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@ -7448,7 +7448,7 @@ static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
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if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
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IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv))
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intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
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ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
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DPFC_CHICKEN_COMP_DUMMY_PIXEL);
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/* Wa_1409825376:tgl (pre-prod)*/
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if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
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@ -7510,7 +7510,7 @@ static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
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* Display WA #0873: cfl
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*/
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intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
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ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
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DPFC_NUKE_ON_ANY_MODIFICATION);
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}
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static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
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@ -7543,7 +7543,7 @@ static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
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* Display WA #0873: kbl
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*/
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intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
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ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
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DPFC_NUKE_ON_ANY_MODIFICATION);
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}
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static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
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@ -7570,14 +7570,14 @@ static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
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* Display WA #0873: skl
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*/
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intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
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ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
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DPFC_NUKE_ON_ANY_MODIFICATION);
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/*
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* WaFbcHighMemBwCorruptionAvoidance:skl
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* Display WA #0883: skl
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*/
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intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
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ILK_DPFC_DISABLE_DUMMY0);
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DPFC_DISABLE_DUMMY0);
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}
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static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
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