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perf vendor events riscv: add T-HEAD C9xx JSON file
Add JSON file of T-HEAD C9xx series events. The event idx (raw value) is summary as following: event id range | support cpu 0x01 - 0x2a | c906,c910,c920 The event ids are based on the public document of T-HEAD and cover the c900 series. These events are the max that c900 series support. Since T-HEAD let manufacturers decide whether events are usable, the final support of the perf events is determined by the pmu node of the soc dtb. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Tested-by: Guo Ren <guoren@kernel.org> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Chen Wang <unicorn_wang@outlook.com> Cc: Ian Rogers <irogers@google.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Jisheng Zhang <jszhang@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Wei Fu <wefu@redhat.com> Cc: linux-riscv@lists.infradead.org Link: https://lore.kernel.org/r/IA1PR20MB495325FCF603BAA841E29281BBBAA@IA1PR20MB4953.namprd20.prod.outlook.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Inochi Amaoto
Arnaldo Carvalho de Melo
parent
19dd49c933
commit
7340c6df49
@ -15,4 +15,5 @@
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#
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#MVENDORID-MARCHID-MIMPID,Version,Filename,EventType
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0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/u74,core
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0x5b7-0x0-0x0,v1,thead/c900-legacy,core
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0x67e-0x80000000db0000[89]0-0x[[:xdigit:]]+,v1,starfive/dubhe-80,core
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@ -0,0 +1,67 @@
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[
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{
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"EventName": "L1_ICACHE_ACCESS",
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"EventCode": "0x00000001",
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"BriefDescription": "L1 instruction cache access"
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},
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{
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"EventName": "L1_ICACHE_MISS",
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"EventCode": "0x00000002",
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"BriefDescription": "L1 instruction cache miss"
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},
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{
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"EventName": "ITLB_MISS",
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"EventCode": "0x00000003",
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"BriefDescription": "I-UTLB miss"
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},
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{
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"EventName": "DTLB_MISS",
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"EventCode": "0x00000004",
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"BriefDescription": "D-UTLB miss"
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},
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{
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"EventName": "JTLB_MISS",
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"EventCode": "0x00000005",
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"BriefDescription": "JTLB miss"
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},
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{
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"EventName": "L1_DCACHE_READ_ACCESS",
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"EventCode": "0x0000000c",
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"BriefDescription": "L1 data cache read access"
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},
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{
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"EventName": "L1_DCACHE_READ_MISS",
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"EventCode": "0x0000000d",
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"BriefDescription": "L1 data cache read miss"
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},
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{
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"EventName": "L1_DCACHE_WRITE_ACCESS",
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"EventCode": "0x0000000e",
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"BriefDescription": "L1 data cache write access"
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},
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{
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"EventName": "L1_DCACHE_WRITE_MISS",
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"EventCode": "0x0000000f",
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"BriefDescription": "L1 data cache write miss"
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},
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{
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"EventName": "LL_CACHE_READ_ACCESS",
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"EventCode": "0x00000010",
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"BriefDescription": "LL Cache read access"
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},
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{
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"EventName": "LL_CACHE_READ_MISS",
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"EventCode": "0x00000011",
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"BriefDescription": "LL Cache read miss"
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},
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{
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"EventName": "LL_CACHE_WRITE_ACCESS",
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"EventCode": "0x00000012",
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"BriefDescription": "LL Cache write access"
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},
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{
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"EventName": "LL_CACHE_WRITE_MISS",
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"EventCode": "0x00000013",
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"BriefDescription": "LL Cache write miss"
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}
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]
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@ -0,0 +1,68 @@
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[
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{
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"ArchStdEvent": "FW_MISALIGNED_LOAD"
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},
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{
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"ArchStdEvent": "FW_MISALIGNED_STORE"
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},
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{
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"ArchStdEvent": "FW_ACCESS_LOAD"
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},
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{
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"ArchStdEvent": "FW_ACCESS_STORE"
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},
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{
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"ArchStdEvent": "FW_ILLEGAL_INSN"
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},
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{
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"ArchStdEvent": "FW_SET_TIMER"
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},
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{
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"ArchStdEvent": "FW_IPI_SENT"
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},
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{
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"ArchStdEvent": "FW_IPI_RECEIVED"
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},
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{
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"ArchStdEvent": "FW_FENCE_I_SENT"
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},
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{
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"ArchStdEvent": "FW_FENCE_I_RECEIVED"
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},
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{
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"ArchStdEvent": "FW_SFENCE_VMA_SENT"
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},
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{
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"ArchStdEvent": "FW_SFENCE_VMA_RECEIVED"
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},
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{
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"ArchStdEvent": "FW_SFENCE_VMA_RECEIVED"
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},
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{
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"ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED"
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},
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{
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"ArchStdEvent": "FW_HFENCE_GVMA_SENT"
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},
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{
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"ArchStdEvent": "FW_HFENCE_GVMA_RECEIVED"
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},
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{
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"ArchStdEvent": "FW_HFENCE_GVMA_VMID_SENT"
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},
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{
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"ArchStdEvent": "FW_HFENCE_GVMA_VMID_RECEIVED"
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},
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{
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"ArchStdEvent": "FW_HFENCE_VVMA_SENT"
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},
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{
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"ArchStdEvent": "FW_HFENCE_VVMA_RECEIVED"
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},
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{
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"ArchStdEvent": "FW_HFENCE_VVMA_ASID_SENT"
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},
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{
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"ArchStdEvent": "FW_HFENCE_VVMA_ASID_RECEIVED"
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}
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]
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@ -0,0 +1,72 @@
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[
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{
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"EventName": "INST_BRANCH_MISPREDICT",
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"EventCode": "0x00000006",
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"BriefDescription": "Mispredicted branch instructions"
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},
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{
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"EventName": "INST_BRANCH",
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"EventCode": "0x00000007",
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"BriefDescription": "Retired branch instructions"
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},
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{
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"EventName": "INST_JMP_MISPREDICT",
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"EventCode": "0x00000008",
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"BriefDescription": "Indirect branch mispredict"
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},
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{
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"EventName": "INST_JMP",
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"EventCode": "0x00000009",
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"BriefDescription": "Retired jmp instructions"
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},
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{
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"EventName": "INST_STORE",
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"EventCode": "0x0000000b",
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"BriefDescription": "Retired store instructions"
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},
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{
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"EventName": "INST_ALU",
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"EventCode": "0x0000001d",
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"BriefDescription": "Retired ALU instructions"
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},
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{
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"EventName": "INST_LDST",
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"EventCode": "0x0000001e",
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"BriefDescription": "Retired Load/Store instructions"
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},
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{
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"EventName": "INST_VECTOR",
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"EventCode": "0x0000001f",
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"BriefDescription": "Retired Vector instructions"
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},
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{
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"EventName": "INST_CSR",
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"EventCode": "0x00000020",
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"BriefDescription": "Retired CSR instructions"
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},
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{
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"EventName": "INST_SYNC",
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"EventCode": "0x00000021",
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"BriefDescription": "Retired sync instructions (AMO/LR/SC instructions)"
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},
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{
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"EventName": "INST_UNALIGNED_ACCESS",
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"EventCode": "0x00000022",
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"BriefDescription": "Retired Store/Load instructions with unaligned memory access"
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},
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{
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"EventName": "INST_ECALL",
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"EventCode": "0x00000025",
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"BriefDescription": "Retired ecall instructions"
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},
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{
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"EventName": "INST_LONG_JP",
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"EventCode": "0x00000026",
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"BriefDescription": "Retired long jump instructions"
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},
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{
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"EventName": "INST_FP",
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"EventCode": "0x0000002a",
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"BriefDescription": "Retired FPU instructions"
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}
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]
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@ -0,0 +1,80 @@
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[
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{
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"EventName": "LSU_SPEC_FAIL",
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"EventCode": "0x0000000a",
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"BriefDescription": "LSU speculation fail"
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},
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{
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"EventName": "IDU_RF_PIPE_FAIL",
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"EventCode": "0x00000014",
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"BriefDescription": "Instruction decode unit launch pipeline failed in RF state"
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},
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{
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"EventName": "IDU_RF_REG_FAIL",
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"EventCode": "0x00000015",
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"BriefDescription": "Instruction decode unit launch register file fail in RF state"
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},
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{
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"EventName": "IDU_RF_INSTRUCTION",
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"EventCode": "0x00000016",
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"BriefDescription": "retired instruction count of Instruction decode unit in RF (Register File) stage"
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},
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{
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"EventName": "LSU_4K_STALL",
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"EventCode": "0x00000017",
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"BriefDescription": "LSU stall times for long distance data access (Over 4K)",
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"PublicDescription": "This stall occurs when translate virtual address with page offset over 4k"
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},
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{
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"EventName": "LSU_OTHER_STALL",
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"EventCode": "0x00000018",
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"BriefDescription": "LSU stall times for other reasons (except the 4k stall)"
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},
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{
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"EventName": "LSU_SQ_OTHER_DIS",
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"EventCode": "0x00000019",
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"BriefDescription": "LSU store queue discard others"
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},
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{
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"EventName": "LSU_SQ_DATA_DISCARD",
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"EventCode": "0x0000001a",
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"BriefDescription": "LSU store queue discard data (uops)"
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},
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{
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"EventName": "BRANCH_DIRECTION_MISPREDICTION",
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"EventCode": "0x0000001b",
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"BriefDescription": "Branch misprediction in BTB"
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},
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{
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"EventName": "BRANCH_DIRECTION_PREDICTION",
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"EventCode": "0x0000001c",
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"BriefDescription": "All branch prediction in BTB",
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"PublicDescription": "This event including both successful prediction and failed prediction in BTB"
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},
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{
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"EventName": "INTERRUPT_ACK_COUNT",
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"EventCode": "0x00000023",
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"BriefDescription": "acknowledged interrupt count"
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},
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{
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"EventName": "INTERRUPT_OFF_CYCLE",
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"EventCode": "0x00000024",
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"BriefDescription": "PLIC arbitration time when the interrupt is not responded",
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"PublicDescription": "The arbitration time is recorded while meeting any of the following:\n- CPU is M-mode and MIE == 0\n- CPU is S-mode and delegation and SIE == 0\n"
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},
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{
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"EventName": "IFU_STALLED_CYCLE",
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"EventCode": "0x00000027",
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"BriefDescription": "Number of stall cycles of the instruction fetch unit (IFU)."
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},
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{
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"EventName": "IDU_STALLED_CYCLE",
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"EventCode": "0x00000028",
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"BriefDescription": "hpcp_backend_stall Number of stall cycles of the instruction decoding unit (IDU) and next-level pipeline unit."
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},
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{
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"EventName": "SYNC_STALL",
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"EventCode": "0x00000029",
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"BriefDescription": "Sync instruction stall cycle fence/fence.i/sync/sfence"
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}
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]
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