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drm/amd/amdgpu: cleanup gfx_v9_0_kiq_init_register()

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Use new WREG32_FIELD macro

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Tom St Denis 2017-04-05 08:59:16 -04:00 committed by Alex Deucher
parent 75bac5c679
commit 72edadd53e
1 changed files with 3 additions and 9 deletions
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12
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
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@ -2020,13 +2020,10 @@ static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
{ {
struct amdgpu_device *adev = ring->adev; struct amdgpu_device *adev = ring->adev;
struct v9_mqd *mqd = ring->mqd_ptr; struct v9_mqd *mqd = ring->mqd_ptr;
uint32_t tmp;
int j; int j;
/* disable wptr polling */ /* disable wptr polling */
tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL)); WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL), tmp);
WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_BASE_ADDR), WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_BASE_ADDR),
mqd->cp_hqd_eop_base_addr_lo); mqd->cp_hqd_eop_base_addr_lo);
@ -2118,11 +2115,8 @@ static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE),
mqd->cp_hqd_active); mqd->cp_hqd_active);
if (ring->use_doorbell) { if (ring->use_doorbell)
tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_STATUS)); WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_STATUS), tmp);
}
return 0; return 0;
} }