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pwm: iqs620a: Fix overflow and optimize calculations
If state->duty_cycle is 0x100000000000000, the previous calculation of
duty_scale overflows and yields a duty cycle ratio of 0% instead of
100%. Fix this by clamping the requested duty cycle to the maximal
possible duty cycle first. This way it is possible to use a native
integer division instead of a (depending on the architecture) more
expensive 64bit division.
With this change in place duty_scale cannot be bigger than 256 which
allows to simplify the calculation of duty_val.
Fixes: 6f0841a819
("pwm: Add support for Azoteq IQS620A PWM generator")
Tested-by: Jeff LaBundy <jeff@labundy.com>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
This commit is contained in:
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@ -46,7 +46,8 @@ static int iqs620_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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{
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struct iqs620_pwm_private *iqs620_pwm;
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struct iqs62x_core *iqs62x;
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u64 duty_scale;
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unsigned int duty_cycle;
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unsigned int duty_scale;
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int ret;
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if (state->polarity != PWM_POLARITY_NORMAL)
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@ -70,7 +71,8 @@ static int iqs620_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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* For lower duty cycles (e.g. 0), the PWM output is simply disabled to
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* allow an external pull-down resistor to hold the GPIO3/LTX pin low.
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*/
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duty_scale = div_u64(state->duty_cycle * 256, IQS620_PWM_PERIOD_NS);
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duty_cycle = min_t(u64, state->duty_cycle, IQS620_PWM_PERIOD_NS);
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duty_scale = duty_cycle * 256 / IQS620_PWM_PERIOD_NS;
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mutex_lock(&iqs620_pwm->lock);
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@ -82,7 +84,7 @@ static int iqs620_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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}
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if (duty_scale) {
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u8 duty_val = min_t(u64, duty_scale - 1, 0xff);
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u8 duty_val = duty_scale - 1;
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ret = regmap_write(iqs62x->regmap, IQS620_PWM_DUTY_CYCLE,
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duty_val);
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