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ath9k_hw: add support for the AR9003 2.2
The checksums of the initvals are: initvals -f ar9003-2p2 0x00000000c2bfa7d5 ar9300_2p2_radio_postamble 0x00000000ada2b114 ar9300Modes_lowest_ob_db_tx_gain_table_2p2 0x00000000e0bc2c84 ar9300Modes_fast_clock_2p2 0x00000000056eaf74 ar9300_2p2_radio_core 0x0000000000000000 ar9300Common_rx_gain_table_merlin_2p2 0x0000000078658fb5 ar9300_2p2_mac_postamble 0x0000000023235333 ar9300_2p2_soc_postamble 0x0000000054d41904 ar9200_merlin_2p2_radio_core 0x000000008475a084 ar9300_2p2_baseband_postamble 0x000000009aaafd90 ar9300_2p2_baseband_core 0x000000003df9a326 ar9300Modes_high_power_tx_gain_table_2p2 0x000000001cfba124 ar9300Modes_high_ob_db_tx_gain_table_2p2 0x0000000011302700 ar9300Common_rx_gain_table_2p2 0x00000000a9a2b114 ar9300Modes_low_ob_db_tx_gain_table_2p2 0x00000000a9d66d40 ar9300_2p2_mac_core 0x000000001e1d0800 ar9300Common_wo_xlna_rx_gain_table_2p2 0x00000000a0c531c8 ar9300_2p2_soc_preamble 0x00000000292e2544 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2 0x000000002d3e2544 ar9300PciePhy_clkreq_enable_L1_2p2 0x00000000293e2544 ar9300PciePhy_clkreq_disable_L1_2p2 Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Luis R. Rodriguez
John W. Linville
parent
53b1b3e1f0
commit
7284635d2d
1785
drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
Normal file
1785
drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
Normal file
File diff suppressed because it is too large
Load Diff
@ -17,6 +17,7 @@
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#include "hw.h"
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#include "ar9003_mac.h"
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#include "ar9003_initvals.h"
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#include "ar9003_2p2_initvals.h"
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/* General hardware code for the AR9003 hadware family */
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@ -31,12 +32,8 @@ static bool ar9003_hw_macversion_supported(u32 macversion)
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return false;
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}
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/* AR9003 2.0 - new INI format (pre, core, post arrays per subsystem) */
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/*
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* XXX: move TX/RX gain INI to its own init_mode_gain_regs after
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* ensuring it does not affect hardware bring up
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*/
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static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
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/* AR9003 2.0 */
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static void ar9003_2p0_hw_init_mode_regs(struct ath_hw *ah)
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{
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/* mac */
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
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@ -106,27 +103,128 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
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3);
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}
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/* AR9003 2.2 */
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static void ar9003_2p2_hw_init_mode_regs(struct ath_hw *ah)
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{
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/* mac */
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
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ar9300_2p2_mac_core,
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ARRAY_SIZE(ar9300_2p2_mac_core), 2);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
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ar9300_2p2_mac_postamble,
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ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
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/* bb */
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
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ar9300_2p2_baseband_core,
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ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
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ar9300_2p2_baseband_postamble,
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ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
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/* radio */
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
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ar9300_2p2_radio_core,
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ARRAY_SIZE(ar9300_2p2_radio_core), 2);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
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ar9300_2p2_radio_postamble,
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ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
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/* soc */
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
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ar9300_2p2_soc_preamble,
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ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
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ar9300_2p2_soc_postamble,
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ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
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/* rx/tx gain */
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9300Common_rx_gain_table_2p2,
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ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
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ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
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5);
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/* Load PCIE SERDES settings from INI */
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/* Awake Setting */
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INIT_INI_ARRAY(&ah->iniPcieSerdes,
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ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
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ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
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2);
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/* Sleep Setting */
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INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
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ar9300PciePhy_clkreq_enable_L1_2p2,
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ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p2),
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2);
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/* Fast clock modal settings */
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INIT_INI_ARRAY(&ah->iniModesAdditional,
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ar9300Modes_fast_clock_2p2,
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ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
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3);
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}
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/*
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* The AR9003 family uses a new INI format (pre, core, post
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* arrays per subsystem).
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*/
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static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
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{
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if (AR_SREV_9300_20(ah))
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ar9003_2p0_hw_init_mode_regs(ah);
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else
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ar9003_2p2_hw_init_mode_regs(ah);
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}
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static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
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{
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switch (ar9003_hw_get_tx_gain_idx(ah)) {
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case 0:
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default:
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9300Modes_lowest_ob_db_tx_gain_table_2p0,
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ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p0),
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5);
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if (AR_SREV_9300_20(ah))
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9300Modes_lowest_ob_db_tx_gain_table_2p0,
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ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p0),
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5);
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else
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
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ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
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5);
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break;
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case 1:
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9300Modes_high_ob_db_tx_gain_table_2p0,
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ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p0),
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5);
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if (AR_SREV_9300_20(ah))
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9300Modes_high_ob_db_tx_gain_table_2p0,
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ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p0),
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5);
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else
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9300Modes_high_ob_db_tx_gain_table_2p2,
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ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p2),
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5);
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break;
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case 2:
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9300Modes_low_ob_db_tx_gain_table_2p0,
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ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p0),
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5);
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if (AR_SREV_9300_20(ah))
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9300Modes_low_ob_db_tx_gain_table_2p0,
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ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p0),
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5);
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else
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9300Modes_low_ob_db_tx_gain_table_2p2,
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ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p2),
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5);
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break;
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}
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}
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@ -136,15 +234,28 @@ static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
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switch (ar9003_hw_get_rx_gain_idx(ah)) {
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case 0:
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default:
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INIT_INI_ARRAY(&ah->iniModesRxGain, ar9300Common_rx_gain_table_2p0,
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ARRAY_SIZE(ar9300Common_rx_gain_table_2p0),
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2);
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if (AR_SREV_9300_20(ah))
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9300Common_rx_gain_table_2p0,
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ARRAY_SIZE(ar9300Common_rx_gain_table_2p0),
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2);
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else
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9300Common_rx_gain_table_2p2,
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ARRAY_SIZE(ar9300Common_rx_gain_table_2p2),
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2);
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break;
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case 1:
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9300Common_wo_xlna_rx_gain_table_2p0,
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ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p0),
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2);
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if (AR_SREV_9300_20(ah))
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9300Common_wo_xlna_rx_gain_table_2p0,
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ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p0),
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2);
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else
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9300Common_wo_xlna_rx_gain_table_2p2,
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ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p2),
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2);
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break;
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}
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}
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