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pinctrl: qcom: Add IPQ5018 pinctrl driver
Add pinctrl definitions for the TLMM of IPQ5018. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Co-developed-by: Nitheesh Sekar <quic_nsekar@quicinc.com> Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com> Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> Link: https://lore.kernel.org/r/20230608122152.3930377-5-quic_srichara@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Sricharan Ramabadhran
Linus Walleij
parent
75750edba5
commit
725d1c8916
@ -39,6 +39,17 @@ config PINCTRL_IPQ4019
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This is the pinctrl, pinmux, pinconf and gpiolib driver for the
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Qualcomm TLMM block found in the Qualcomm IPQ4019 platform.
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config PINCTRL_IPQ5018
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tristate "Qualcomm Technologies, Inc. IPQ5018 pin controller driver"
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depends on OF || COMPILE_TEST
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depends on ARM64 || COMPILE_TEST
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select PINCTRL_MSM
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help
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This is the pinctrl, pinmux, pinconf and gpiolib driver for
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the Qualcomm Technologies Inc. TLMM block found on the
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Qualcomm Technologies Inc. IPQ5018 platform. Select this for
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IPQ5018.
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config PINCTRL_IPQ8064
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tristate "Qualcomm IPQ8064 pin controller driver"
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depends on OF
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@ -4,6 +4,7 @@ obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o
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obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o
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obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o
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obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o
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obj-$(CONFIG_PINCTRL_IPQ5018) += pinctrl-ipq5018.o
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obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
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obj-$(CONFIG_PINCTRL_IPQ5332) += pinctrl-ipq5332.o
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obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o
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783
drivers/pinctrl/qcom/pinctrl-ipq5018.c
Normal file
783
drivers/pinctrl/qcom/pinctrl-ipq5018.c
Normal file
@ -0,0 +1,783 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2019-2021, 2023 The Linux Foundation. All rights reserved.
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*/
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/platform_device.h>
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#include "pinctrl-msm.h"
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#define REG_SIZE 0x1000
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#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
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{ \
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.grp = PINCTRL_PINGROUP("gpio" #id, \
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gpio##id##_pins, \
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ARRAY_SIZE(gpio##id##_pins)), \
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.funcs = (int[]){ \
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msm_mux_gpio, /* gpio mode */ \
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msm_mux_##f1, \
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msm_mux_##f2, \
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msm_mux_##f3, \
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msm_mux_##f4, \
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msm_mux_##f5, \
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msm_mux_##f6, \
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msm_mux_##f7, \
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msm_mux_##f8, \
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msm_mux_##f9 \
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}, \
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.nfuncs = 10, \
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.ctl_reg = REG_SIZE * id, \
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.io_reg = 0x4 + REG_SIZE * id, \
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.intr_cfg_reg = 0x8 + REG_SIZE * id, \
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.intr_status_reg = 0xc + REG_SIZE * id, \
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.intr_target_reg = 0x8 + REG_SIZE * id, \
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.mux_bit = 2, \
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.pull_bit = 0, \
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.drv_bit = 6, \
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.oe_bit = 9, \
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.in_bit = 0, \
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.out_bit = 1, \
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.intr_enable_bit = 0, \
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.intr_status_bit = 0, \
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.intr_target_bit = 5, \
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.intr_target_kpss_val = 3, \
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.intr_raw_status_bit = 4, \
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.intr_polarity_bit = 1, \
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.intr_detection_bit = 2, \
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.intr_detection_width = 2, \
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}
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static const struct pinctrl_pin_desc ipq5018_pins[] = {
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PINCTRL_PIN(0, "GPIO_0"),
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PINCTRL_PIN(1, "GPIO_1"),
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PINCTRL_PIN(2, "GPIO_2"),
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PINCTRL_PIN(3, "GPIO_3"),
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PINCTRL_PIN(4, "GPIO_4"),
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PINCTRL_PIN(5, "GPIO_5"),
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PINCTRL_PIN(6, "GPIO_6"),
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PINCTRL_PIN(7, "GPIO_7"),
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PINCTRL_PIN(8, "GPIO_8"),
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PINCTRL_PIN(9, "GPIO_9"),
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PINCTRL_PIN(10, "GPIO_10"),
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PINCTRL_PIN(11, "GPIO_11"),
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PINCTRL_PIN(12, "GPIO_12"),
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PINCTRL_PIN(13, "GPIO_13"),
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PINCTRL_PIN(14, "GPIO_14"),
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PINCTRL_PIN(15, "GPIO_15"),
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PINCTRL_PIN(16, "GPIO_16"),
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PINCTRL_PIN(17, "GPIO_17"),
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PINCTRL_PIN(18, "GPIO_18"),
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PINCTRL_PIN(19, "GPIO_19"),
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PINCTRL_PIN(20, "GPIO_20"),
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PINCTRL_PIN(21, "GPIO_21"),
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PINCTRL_PIN(22, "GPIO_22"),
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PINCTRL_PIN(23, "GPIO_23"),
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PINCTRL_PIN(24, "GPIO_24"),
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PINCTRL_PIN(25, "GPIO_25"),
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PINCTRL_PIN(26, "GPIO_26"),
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PINCTRL_PIN(27, "GPIO_27"),
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PINCTRL_PIN(28, "GPIO_28"),
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PINCTRL_PIN(29, "GPIO_29"),
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PINCTRL_PIN(30, "GPIO_30"),
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PINCTRL_PIN(31, "GPIO_31"),
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PINCTRL_PIN(32, "GPIO_32"),
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PINCTRL_PIN(33, "GPIO_33"),
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PINCTRL_PIN(34, "GPIO_34"),
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PINCTRL_PIN(35, "GPIO_35"),
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PINCTRL_PIN(36, "GPIO_36"),
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PINCTRL_PIN(37, "GPIO_37"),
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PINCTRL_PIN(38, "GPIO_38"),
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PINCTRL_PIN(39, "GPIO_39"),
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PINCTRL_PIN(40, "GPIO_40"),
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PINCTRL_PIN(41, "GPIO_41"),
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PINCTRL_PIN(42, "GPIO_42"),
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PINCTRL_PIN(43, "GPIO_43"),
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PINCTRL_PIN(44, "GPIO_44"),
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PINCTRL_PIN(45, "GPIO_45"),
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PINCTRL_PIN(46, "GPIO_46"),
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};
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#define DECLARE_MSM_GPIO_PINS(pin) \
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static const unsigned int gpio##pin##_pins[] = { pin }
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DECLARE_MSM_GPIO_PINS(0);
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DECLARE_MSM_GPIO_PINS(1);
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DECLARE_MSM_GPIO_PINS(2);
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DECLARE_MSM_GPIO_PINS(3);
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DECLARE_MSM_GPIO_PINS(4);
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DECLARE_MSM_GPIO_PINS(5);
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DECLARE_MSM_GPIO_PINS(6);
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DECLARE_MSM_GPIO_PINS(7);
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DECLARE_MSM_GPIO_PINS(8);
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DECLARE_MSM_GPIO_PINS(9);
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DECLARE_MSM_GPIO_PINS(10);
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DECLARE_MSM_GPIO_PINS(11);
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DECLARE_MSM_GPIO_PINS(12);
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DECLARE_MSM_GPIO_PINS(13);
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DECLARE_MSM_GPIO_PINS(14);
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DECLARE_MSM_GPIO_PINS(15);
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DECLARE_MSM_GPIO_PINS(16);
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DECLARE_MSM_GPIO_PINS(17);
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DECLARE_MSM_GPIO_PINS(18);
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DECLARE_MSM_GPIO_PINS(19);
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DECLARE_MSM_GPIO_PINS(20);
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DECLARE_MSM_GPIO_PINS(21);
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DECLARE_MSM_GPIO_PINS(22);
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DECLARE_MSM_GPIO_PINS(23);
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DECLARE_MSM_GPIO_PINS(24);
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DECLARE_MSM_GPIO_PINS(25);
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DECLARE_MSM_GPIO_PINS(26);
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DECLARE_MSM_GPIO_PINS(27);
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DECLARE_MSM_GPIO_PINS(28);
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DECLARE_MSM_GPIO_PINS(29);
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DECLARE_MSM_GPIO_PINS(30);
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DECLARE_MSM_GPIO_PINS(31);
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DECLARE_MSM_GPIO_PINS(32);
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DECLARE_MSM_GPIO_PINS(33);
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DECLARE_MSM_GPIO_PINS(34);
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DECLARE_MSM_GPIO_PINS(35);
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DECLARE_MSM_GPIO_PINS(36);
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DECLARE_MSM_GPIO_PINS(37);
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DECLARE_MSM_GPIO_PINS(38);
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DECLARE_MSM_GPIO_PINS(39);
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DECLARE_MSM_GPIO_PINS(40);
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DECLARE_MSM_GPIO_PINS(41);
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DECLARE_MSM_GPIO_PINS(42);
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DECLARE_MSM_GPIO_PINS(43);
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DECLARE_MSM_GPIO_PINS(44);
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DECLARE_MSM_GPIO_PINS(45);
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DECLARE_MSM_GPIO_PINS(46);
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enum ipq5018_functions {
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msm_mux_atest_char,
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msm_mux_audio_pdm0,
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msm_mux_audio_pdm1,
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msm_mux_audio_rxbclk,
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msm_mux_audio_rxd,
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msm_mux_audio_rxfsync,
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msm_mux_audio_rxmclk,
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msm_mux_audio_txbclk,
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msm_mux_audio_txd,
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msm_mux_audio_txfsync,
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msm_mux_audio_txmclk,
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msm_mux_blsp0_i2c,
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msm_mux_blsp0_spi,
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msm_mux_blsp0_uart0,
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msm_mux_blsp0_uart1,
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msm_mux_blsp1_i2c0,
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msm_mux_blsp1_i2c1,
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msm_mux_blsp1_spi0,
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msm_mux_blsp1_spi1,
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msm_mux_blsp1_uart0,
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msm_mux_blsp1_uart1,
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msm_mux_blsp1_uart2,
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msm_mux_blsp2_i2c0,
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msm_mux_blsp2_i2c1,
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msm_mux_blsp2_spi,
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msm_mux_blsp2_spi0,
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msm_mux_blsp2_spi1,
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msm_mux_btss,
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msm_mux_burn0,
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msm_mux_burn1,
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msm_mux_cri_trng,
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msm_mux_cri_trng0,
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msm_mux_cri_trng1,
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msm_mux_cxc_clk,
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msm_mux_cxc_data,
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msm_mux_dbg_out,
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msm_mux_eud_gpio,
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msm_mux_gcc_plltest,
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msm_mux_gcc_tlmm,
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msm_mux_gpio,
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msm_mux_led0,
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msm_mux_led2,
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msm_mux_mac0,
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msm_mux_mac1,
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msm_mux_mdc,
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msm_mux_mdio,
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msm_mux_pcie0_clk,
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msm_mux_pcie0_wake,
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msm_mux_pcie1_clk,
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msm_mux_pcie1_wake,
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msm_mux_pll_test,
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msm_mux_prng_rosc,
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msm_mux_pwm0,
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msm_mux_pwm1,
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msm_mux_pwm2,
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msm_mux_pwm3,
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msm_mux_qdss_cti_trig_in_a0,
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msm_mux_qdss_cti_trig_in_a1,
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msm_mux_qdss_cti_trig_in_b0,
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msm_mux_qdss_cti_trig_in_b1,
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msm_mux_qdss_cti_trig_out_a0,
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msm_mux_qdss_cti_trig_out_a1,
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msm_mux_qdss_cti_trig_out_b0,
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msm_mux_qdss_cti_trig_out_b1,
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msm_mux_qdss_traceclk_a,
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msm_mux_qdss_traceclk_b,
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msm_mux_qdss_tracectl_a,
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msm_mux_qdss_tracectl_b,
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msm_mux_qdss_tracedata_a,
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msm_mux_qdss_tracedata_b,
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msm_mux_qspi_clk,
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msm_mux_qspi_cs,
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msm_mux_qspi_data,
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msm_mux_reset_out,
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msm_mux_sdc1_clk,
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msm_mux_sdc1_cmd,
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msm_mux_sdc1_data,
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msm_mux_wci_txd,
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msm_mux_wci_rxd,
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msm_mux_wsa_swrm,
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msm_mux_wsi_clk3,
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msm_mux_wsi_data3,
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msm_mux_wsis_reset,
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msm_mux_xfem,
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msm_mux__,
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};
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static const char * const atest_char_groups[] = {
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"gpio0", "gpio1", "gpio2", "gpio3", "gpio37",
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};
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static const char * const _groups[] = {
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"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
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"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
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"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
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"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
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"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
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"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
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"gpio43", "gpio44", "gpio45", "gpio46",
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};
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static const char * const wci_txd_groups[] = {
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"gpio0", "gpio1", "gpio2", "gpio3",
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"gpio42", "gpio43", "gpio44", "gpio45",
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};
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static const char * const wci_rxd_groups[] = {
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"gpio0", "gpio1", "gpio2", "gpio3",
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"gpio42", "gpio43", "gpio44", "gpio45",
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};
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static const char * const xfem_groups[] = {
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"gpio0", "gpio1", "gpio2", "gpio3",
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"gpio42", "gpio43", "gpio44", "gpio45",
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};
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static const char * const qdss_cti_trig_out_a0_groups[] = {
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"gpio0",
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};
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static const char * const qdss_cti_trig_in_a0_groups[] = {
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"gpio1",
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};
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static const char * const qdss_cti_trig_out_a1_groups[] = {
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"gpio2",
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};
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static const char * const qdss_cti_trig_in_a1_groups[] = {
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"gpio3",
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};
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static const char * const sdc1_data_groups[] = {
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"gpio4", "gpio5", "gpio6", "gpio7",
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};
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static const char * const qspi_data_groups[] = {
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"gpio4",
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"gpio5",
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"gpio6",
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"gpio7",
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};
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static const char * const blsp1_spi1_groups[] = {
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"gpio4", "gpio5", "gpio6", "gpio7",
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};
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static const char * const btss_groups[] = {
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"gpio4", "gpio5", "gpio6", "gpio7", "gpio8", "gpio17", "gpio18",
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"gpio19", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
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};
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static const char * const dbg_out_groups[] = {
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"gpio4",
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};
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static const char * const qdss_traceclk_a_groups[] = {
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"gpio4",
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};
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static const char * const burn0_groups[] = {
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"gpio4",
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};
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static const char * const cxc_clk_groups[] = {
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"gpio5",
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};
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static const char * const blsp1_i2c1_groups[] = {
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"gpio5", "gpio6",
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};
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static const char * const qdss_tracectl_a_groups[] = {
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"gpio5",
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};
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static const char * const burn1_groups[] = {
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"gpio5",
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};
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static const char * const cxc_data_groups[] = {
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"gpio6",
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};
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static const char * const qdss_tracedata_a_groups[] = {
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"gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12",
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"gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19",
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"gpio20", "gpio21",
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};
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static const char * const mac0_groups[] = {
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"gpio7",
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};
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static const char * const sdc1_cmd_groups[] = {
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"gpio8",
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};
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static const char * const qspi_cs_groups[] = {
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"gpio8",
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};
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static const char * const mac1_groups[] = {
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"gpio8",
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};
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static const char * const sdc1_clk_groups[] = {
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"gpio9",
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};
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static const char * const qspi_clk_groups[] = {
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"gpio9",
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};
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static const char * const blsp0_spi_groups[] = {
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"gpio10", "gpio11", "gpio12", "gpio13",
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};
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static const char * const blsp1_uart0_groups[] = {
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"gpio10", "gpio11", "gpio12", "gpio13",
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};
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static const char * const gcc_plltest_groups[] = {
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"gpio10", "gpio12",
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};
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static const char * const gcc_tlmm_groups[] = {
|
||||
"gpio11",
|
||||
};
|
||||
|
||||
static const char * const blsp0_i2c_groups[] = {
|
||||
"gpio12", "gpio13",
|
||||
};
|
||||
|
||||
static const char * const pcie0_clk_groups[] = {
|
||||
"gpio14",
|
||||
};
|
||||
|
||||
static const char * const cri_trng0_groups[] = {
|
||||
"gpio14",
|
||||
};
|
||||
|
||||
static const char * const cri_trng1_groups[] = {
|
||||
"gpio15",
|
||||
};
|
||||
|
||||
static const char * const pcie0_wake_groups[] = {
|
||||
"gpio16",
|
||||
};
|
||||
|
||||
static const char * const cri_trng_groups[] = {
|
||||
"gpio16",
|
||||
};
|
||||
|
||||
static const char * const pcie1_clk_groups[] = {
|
||||
"gpio17",
|
||||
};
|
||||
|
||||
static const char * const prng_rosc_groups[] = {
|
||||
"gpio17",
|
||||
};
|
||||
|
||||
static const char * const blsp1_spi0_groups[] = {
|
||||
"gpio18", "gpio19", "gpio20", "gpio21",
|
||||
};
|
||||
|
||||
static const char * const pcie1_wake_groups[] = {
|
||||
"gpio19",
|
||||
};
|
||||
|
||||
static const char * const blsp1_i2c0_groups[] = {
|
||||
"gpio19", "gpio20",
|
||||
};
|
||||
|
||||
static const char * const blsp0_uart0_groups[] = {
|
||||
"gpio20", "gpio21",
|
||||
};
|
||||
|
||||
static const char * const pll_test_groups[] = {
|
||||
"gpio22",
|
||||
};
|
||||
|
||||
static const char * const eud_gpio_groups[] = {
|
||||
"gpio22", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
|
||||
};
|
||||
|
||||
static const char * const audio_rxmclk_groups[] = {
|
||||
"gpio23", "gpio23",
|
||||
};
|
||||
|
||||
static const char * const audio_pdm0_groups[] = {
|
||||
"gpio23", "gpio24",
|
||||
};
|
||||
|
||||
static const char * const blsp2_spi1_groups[] = {
|
||||
"gpio23", "gpio24", "gpio25", "gpio26",
|
||||
};
|
||||
|
||||
static const char * const blsp1_uart2_groups[] = {
|
||||
"gpio23", "gpio24", "gpio25", "gpio26",
|
||||
};
|
||||
|
||||
static const char * const qdss_tracedata_b_groups[] = {
|
||||
"gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
|
||||
"gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
|
||||
"gpio37", "gpio38",
|
||||
};
|
||||
|
||||
static const char * const audio_rxbclk_groups[] = {
|
||||
"gpio24",
|
||||
};
|
||||
|
||||
static const char * const audio_rxfsync_groups[] = {
|
||||
"gpio25",
|
||||
};
|
||||
|
||||
static const char * const audio_pdm1_groups[] = {
|
||||
"gpio25", "gpio26",
|
||||
};
|
||||
|
||||
static const char * const blsp2_i2c1_groups[] = {
|
||||
"gpio25", "gpio26",
|
||||
};
|
||||
|
||||
static const char * const audio_rxd_groups[] = {
|
||||
"gpio26",
|
||||
};
|
||||
|
||||
static const char * const audio_txmclk_groups[] = {
|
||||
"gpio27", "gpio27",
|
||||
};
|
||||
|
||||
static const char * const wsa_swrm_groups[] = {
|
||||
"gpio27", "gpio28",
|
||||
};
|
||||
|
||||
static const char * const blsp2_spi_groups[] = {
|
||||
"gpio27",
|
||||
};
|
||||
|
||||
static const char * const audio_txbclk_groups[] = {
|
||||
"gpio28",
|
||||
};
|
||||
|
||||
static const char * const blsp0_uart1_groups[] = {
|
||||
"gpio28", "gpio29",
|
||||
};
|
||||
|
||||
static const char * const audio_txfsync_groups[] = {
|
||||
"gpio29",
|
||||
};
|
||||
|
||||
static const char * const audio_txd_groups[] = {
|
||||
"gpio30",
|
||||
};
|
||||
|
||||
static const char * const wsis_reset_groups[] = {
|
||||
"gpio30",
|
||||
};
|
||||
|
||||
static const char * const blsp2_spi0_groups[] = {
|
||||
"gpio31", "gpio32", "gpio33", "gpio34",
|
||||
};
|
||||
|
||||
static const char * const blsp1_uart1_groups[] = {
|
||||
"gpio31", "gpio32", "gpio33", "gpio34",
|
||||
};
|
||||
|
||||
static const char * const blsp2_i2c0_groups[] = {
|
||||
"gpio33", "gpio34",
|
||||
};
|
||||
|
||||
static const char * const mdc_groups[] = {
|
||||
"gpio36",
|
||||
};
|
||||
|
||||
static const char * const wsi_clk3_groups[] = {
|
||||
"gpio36",
|
||||
};
|
||||
|
||||
static const char * const mdio_groups[] = {
|
||||
"gpio37",
|
||||
};
|
||||
|
||||
static const char * const wsi_data3_groups[] = {
|
||||
"gpio37",
|
||||
};
|
||||
|
||||
static const char * const qdss_traceclk_b_groups[] = {
|
||||
"gpio39",
|
||||
};
|
||||
|
||||
static const char * const reset_out_groups[] = {
|
||||
"gpio40",
|
||||
};
|
||||
|
||||
static const char * const qdss_tracectl_b_groups[] = {
|
||||
"gpio40",
|
||||
};
|
||||
|
||||
static const char * const pwm0_groups[] = {
|
||||
"gpio42",
|
||||
};
|
||||
|
||||
static const char * const qdss_cti_trig_out_b0_groups[] = {
|
||||
"gpio42",
|
||||
};
|
||||
|
||||
static const char * const pwm1_groups[] = {
|
||||
"gpio43",
|
||||
};
|
||||
|
||||
static const char * const qdss_cti_trig_in_b0_groups[] = {
|
||||
"gpio43",
|
||||
};
|
||||
|
||||
static const char * const pwm2_groups[] = {
|
||||
"gpio44",
|
||||
};
|
||||
|
||||
static const char * const qdss_cti_trig_out_b1_groups[] = {
|
||||
"gpio44",
|
||||
};
|
||||
|
||||
static const char * const pwm3_groups[] = {
|
||||
"gpio45",
|
||||
};
|
||||
|
||||
static const char * const qdss_cti_trig_in_b1_groups[] = {
|
||||
"gpio45",
|
||||
};
|
||||
|
||||
static const char * const led0_groups[] = {
|
||||
"gpio46", "gpio30", "gpio10",
|
||||
};
|
||||
|
||||
static const char * const led2_groups[] = {
|
||||
"gpio30",
|
||||
};
|
||||
|
||||
static const char * const gpio_groups[] = {
|
||||
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
|
||||
"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
|
||||
"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
|
||||
"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
|
||||
"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
|
||||
"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
|
||||
"gpio43", "gpio44", "gpio45", "gpio46",
|
||||
};
|
||||
|
||||
static const struct pinfunction ipq5018_functions[] = {
|
||||
MSM_PIN_FUNCTION(atest_char),
|
||||
MSM_PIN_FUNCTION(audio_pdm0),
|
||||
MSM_PIN_FUNCTION(audio_pdm1),
|
||||
MSM_PIN_FUNCTION(audio_rxbclk),
|
||||
MSM_PIN_FUNCTION(audio_rxd),
|
||||
MSM_PIN_FUNCTION(audio_rxfsync),
|
||||
MSM_PIN_FUNCTION(audio_rxmclk),
|
||||
MSM_PIN_FUNCTION(audio_txbclk),
|
||||
MSM_PIN_FUNCTION(audio_txd),
|
||||
MSM_PIN_FUNCTION(audio_txfsync),
|
||||
MSM_PIN_FUNCTION(audio_txmclk),
|
||||
MSM_PIN_FUNCTION(blsp0_i2c),
|
||||
MSM_PIN_FUNCTION(blsp0_spi),
|
||||
MSM_PIN_FUNCTION(blsp0_uart0),
|
||||
MSM_PIN_FUNCTION(blsp0_uart1),
|
||||
MSM_PIN_FUNCTION(blsp1_i2c0),
|
||||
MSM_PIN_FUNCTION(blsp1_i2c1),
|
||||
MSM_PIN_FUNCTION(blsp1_spi0),
|
||||
MSM_PIN_FUNCTION(blsp1_spi1),
|
||||
MSM_PIN_FUNCTION(blsp1_uart0),
|
||||
MSM_PIN_FUNCTION(blsp1_uart1),
|
||||
MSM_PIN_FUNCTION(blsp1_uart2),
|
||||
MSM_PIN_FUNCTION(blsp2_i2c0),
|
||||
MSM_PIN_FUNCTION(blsp2_i2c1),
|
||||
MSM_PIN_FUNCTION(blsp2_spi),
|
||||
MSM_PIN_FUNCTION(blsp2_spi0),
|
||||
MSM_PIN_FUNCTION(blsp2_spi1),
|
||||
MSM_PIN_FUNCTION(btss),
|
||||
MSM_PIN_FUNCTION(burn0),
|
||||
MSM_PIN_FUNCTION(burn1),
|
||||
MSM_PIN_FUNCTION(cri_trng),
|
||||
MSM_PIN_FUNCTION(cri_trng0),
|
||||
MSM_PIN_FUNCTION(cri_trng1),
|
||||
MSM_PIN_FUNCTION(cxc_clk),
|
||||
MSM_PIN_FUNCTION(cxc_data),
|
||||
MSM_PIN_FUNCTION(dbg_out),
|
||||
MSM_PIN_FUNCTION(eud_gpio),
|
||||
MSM_PIN_FUNCTION(gcc_plltest),
|
||||
MSM_PIN_FUNCTION(gcc_tlmm),
|
||||
MSM_PIN_FUNCTION(gpio),
|
||||
MSM_PIN_FUNCTION(led0),
|
||||
MSM_PIN_FUNCTION(led2),
|
||||
MSM_PIN_FUNCTION(mac0),
|
||||
MSM_PIN_FUNCTION(mac1),
|
||||
MSM_PIN_FUNCTION(mdc),
|
||||
MSM_PIN_FUNCTION(mdio),
|
||||
MSM_PIN_FUNCTION(pcie0_clk),
|
||||
MSM_PIN_FUNCTION(pcie0_wake),
|
||||
MSM_PIN_FUNCTION(pcie1_clk),
|
||||
MSM_PIN_FUNCTION(pcie1_wake),
|
||||
MSM_PIN_FUNCTION(pll_test),
|
||||
MSM_PIN_FUNCTION(prng_rosc),
|
||||
MSM_PIN_FUNCTION(pwm0),
|
||||
MSM_PIN_FUNCTION(pwm1),
|
||||
MSM_PIN_FUNCTION(pwm2),
|
||||
MSM_PIN_FUNCTION(pwm3),
|
||||
MSM_PIN_FUNCTION(qdss_cti_trig_in_a0),
|
||||
MSM_PIN_FUNCTION(qdss_cti_trig_in_a1),
|
||||
MSM_PIN_FUNCTION(qdss_cti_trig_in_b0),
|
||||
MSM_PIN_FUNCTION(qdss_cti_trig_in_b1),
|
||||
MSM_PIN_FUNCTION(qdss_cti_trig_out_a0),
|
||||
MSM_PIN_FUNCTION(qdss_cti_trig_out_a1),
|
||||
MSM_PIN_FUNCTION(qdss_cti_trig_out_b0),
|
||||
MSM_PIN_FUNCTION(qdss_cti_trig_out_b1),
|
||||
MSM_PIN_FUNCTION(qdss_traceclk_a),
|
||||
MSM_PIN_FUNCTION(qdss_traceclk_b),
|
||||
MSM_PIN_FUNCTION(qdss_tracectl_a),
|
||||
MSM_PIN_FUNCTION(qdss_tracectl_b),
|
||||
MSM_PIN_FUNCTION(qdss_tracedata_a),
|
||||
MSM_PIN_FUNCTION(qdss_tracedata_b),
|
||||
MSM_PIN_FUNCTION(qspi_clk),
|
||||
MSM_PIN_FUNCTION(qspi_cs),
|
||||
MSM_PIN_FUNCTION(qspi_data),
|
||||
MSM_PIN_FUNCTION(reset_out),
|
||||
MSM_PIN_FUNCTION(sdc1_clk),
|
||||
MSM_PIN_FUNCTION(sdc1_cmd),
|
||||
MSM_PIN_FUNCTION(sdc1_data),
|
||||
MSM_PIN_FUNCTION(wci_txd),
|
||||
MSM_PIN_FUNCTION(wci_rxd),
|
||||
MSM_PIN_FUNCTION(wsa_swrm),
|
||||
MSM_PIN_FUNCTION(wsi_clk3),
|
||||
MSM_PIN_FUNCTION(wsi_data3),
|
||||
MSM_PIN_FUNCTION(wsis_reset),
|
||||
MSM_PIN_FUNCTION(xfem),
|
||||
};
|
||||
|
||||
static const struct msm_pingroup ipq5018_groups[] = {
|
||||
PINGROUP(0, atest_char, _, qdss_cti_trig_out_a0, wci_txd, wci_rxd, xfem, _, _, _),
|
||||
PINGROUP(1, atest_char, _, qdss_cti_trig_in_a0, wci_txd, wci_rxd, xfem, _, _, _),
|
||||
PINGROUP(2, atest_char, _, qdss_cti_trig_out_a1, wci_txd, wci_rxd, xfem, _, _, _),
|
||||
PINGROUP(3, atest_char, _, qdss_cti_trig_in_a1, wci_txd, wci_rxd, xfem, _, _, _),
|
||||
PINGROUP(4, sdc1_data, qspi_data, blsp1_spi1, btss, dbg_out, qdss_traceclk_a, _, burn0, _),
|
||||
PINGROUP(5, sdc1_data, qspi_data, cxc_clk, blsp1_spi1, blsp1_i2c1, btss, _, qdss_tracectl_a, _),
|
||||
PINGROUP(6, sdc1_data, qspi_data, cxc_data, blsp1_spi1, blsp1_i2c1, btss, _, qdss_tracedata_a, _),
|
||||
PINGROUP(7, sdc1_data, qspi_data, mac0, blsp1_spi1, btss, _, qdss_tracedata_a, _, _),
|
||||
PINGROUP(8, sdc1_cmd, qspi_cs, mac1, btss, _, qdss_tracedata_a, _, _, _),
|
||||
PINGROUP(9, sdc1_clk, qspi_clk, _, qdss_tracedata_a, _, _, _, _, _),
|
||||
PINGROUP(10, blsp0_spi, blsp1_uart0, led0, gcc_plltest, qdss_tracedata_a, _, _, _, _),
|
||||
PINGROUP(11, blsp0_spi, blsp1_uart0, _, gcc_tlmm, qdss_tracedata_a, _, _, _, _),
|
||||
PINGROUP(12, blsp0_spi, blsp0_i2c, blsp1_uart0, _, gcc_plltest, qdss_tracedata_a, _, _, _),
|
||||
PINGROUP(13, blsp0_spi, blsp0_i2c, blsp1_uart0, _, qdss_tracedata_a, _, _, _, _),
|
||||
PINGROUP(14, pcie0_clk, _, _, cri_trng0, qdss_tracedata_a, _, _, _, _),
|
||||
PINGROUP(15, _, _, cri_trng1, qdss_tracedata_a, _, _, _, _, _),
|
||||
PINGROUP(16, pcie0_wake, _, _, cri_trng, qdss_tracedata_a, _, _, _, _),
|
||||
PINGROUP(17, pcie1_clk, btss, _, prng_rosc, qdss_tracedata_a, _, _, _, _),
|
||||
PINGROUP(18, blsp1_spi0, btss, _, qdss_tracedata_a, _, _, _, _, _),
|
||||
PINGROUP(19, pcie1_wake, blsp1_spi0, blsp1_i2c0, btss, _, qdss_tracedata_a, _, _, _),
|
||||
PINGROUP(20, blsp0_uart0, blsp1_spi0, blsp1_i2c0, _, qdss_tracedata_a, _, _, _, _),
|
||||
PINGROUP(21, blsp0_uart0, blsp1_spi0, _, qdss_tracedata_a, _, _, _, _, _),
|
||||
PINGROUP(22, _, pll_test, eud_gpio, _, _, _, _, _, _),
|
||||
PINGROUP(23, audio_rxmclk, audio_pdm0, audio_rxmclk, blsp2_spi1, blsp1_uart2, btss, _, qdss_tracedata_b, _),
|
||||
PINGROUP(24, audio_rxbclk, audio_pdm0, blsp2_spi1, blsp1_uart2, btss, _, qdss_tracedata_b, _, _),
|
||||
PINGROUP(25, audio_rxfsync, audio_pdm1, blsp2_i2c1, blsp2_spi1, blsp1_uart2, btss, _, qdss_tracedata_b, _),
|
||||
PINGROUP(26, audio_rxd, audio_pdm1, blsp2_i2c1, blsp2_spi1, blsp1_uart2, btss, _, qdss_tracedata_b, _),
|
||||
PINGROUP(27, audio_txmclk, wsa_swrm, audio_txmclk, blsp2_spi, btss, _, qdss_tracedata_b, _, _),
|
||||
PINGROUP(28, audio_txbclk, wsa_swrm, blsp0_uart1, btss, qdss_tracedata_b, _, _, _, _),
|
||||
PINGROUP(29, audio_txfsync, _, blsp0_uart1, _, qdss_tracedata_b, _, _, _, _),
|
||||
PINGROUP(30, audio_txd, led2, led0, _, _, _, _, _, _),
|
||||
PINGROUP(31, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b, eud_gpio, _, _, _, _),
|
||||
PINGROUP(32, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b, eud_gpio, _, _, _, _),
|
||||
PINGROUP(33, blsp2_i2c0, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b, eud_gpio, _, _, _),
|
||||
PINGROUP(34, blsp2_i2c0, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b, eud_gpio, _, _, _),
|
||||
PINGROUP(35, _, qdss_tracedata_b, eud_gpio, _, _, _, _, _, _),
|
||||
PINGROUP(36, mdc, qdss_tracedata_b, _, wsi_clk3, _, _, _, _, _),
|
||||
PINGROUP(37, mdio, atest_char, qdss_tracedata_b, _, wsi_data3, _, _, _, _),
|
||||
PINGROUP(38, qdss_tracedata_b, _, _, _, _, _, _, _, _),
|
||||
PINGROUP(39, qdss_traceclk_b, _, _, _, _, _, _, _, _),
|
||||
PINGROUP(40, reset_out, qdss_tracectl_b, _, _, _, _, _, _, _),
|
||||
PINGROUP(41, _, _, _, _, _, _, _, _, _),
|
||||
PINGROUP(42, pwm0, qdss_cti_trig_out_b0, wci_txd, wci_rxd, xfem, _, _, _, _),
|
||||
PINGROUP(43, pwm1, qdss_cti_trig_in_b0, wci_txd, wci_rxd, xfem, _, _, _, _),
|
||||
PINGROUP(44, pwm2, qdss_cti_trig_out_b1, wci_txd, wci_rxd, xfem, _, _, _, _),
|
||||
PINGROUP(45, pwm3, qdss_cti_trig_in_b1, wci_txd, wci_rxd, xfem, _, _, _, _),
|
||||
PINGROUP(46, led0, _, _, _, _, _, _, _, _),
|
||||
};
|
||||
|
||||
static const struct msm_pinctrl_soc_data ipq5018_pinctrl = {
|
||||
.pins = ipq5018_pins,
|
||||
.npins = ARRAY_SIZE(ipq5018_pins),
|
||||
.functions = ipq5018_functions,
|
||||
.nfunctions = ARRAY_SIZE(ipq5018_functions),
|
||||
.groups = ipq5018_groups,
|
||||
.ngroups = ARRAY_SIZE(ipq5018_groups),
|
||||
.ngpios = 47,
|
||||
};
|
||||
|
||||
static int ipq5018_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
return msm_pinctrl_probe(pdev, &ipq5018_pinctrl);
|
||||
}
|
||||
|
||||
static const struct of_device_id ipq5018_pinctrl_of_match[] = {
|
||||
{ .compatible = "qcom,ipq5018-tlmm", },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, ipq5018_pinctrl_of_match);
|
||||
|
||||
static struct platform_driver ipq5018_pinctrl_driver = {
|
||||
.driver = {
|
||||
.name = "ipq5018-tlmm",
|
||||
.of_match_table = ipq5018_pinctrl_of_match,
|
||||
},
|
||||
.probe = ipq5018_pinctrl_probe,
|
||||
.remove = msm_pinctrl_remove,
|
||||
};
|
||||
|
||||
static int __init ipq5018_pinctrl_init(void)
|
||||
{
|
||||
return platform_driver_register(&ipq5018_pinctrl_driver);
|
||||
}
|
||||
arch_initcall(ipq5018_pinctrl_init);
|
||||
|
||||
static void __exit ipq5018_pinctrl_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&ipq5018_pinctrl_driver);
|
||||
}
|
||||
module_exit(ipq5018_pinctrl_exit);
|
||||
|
||||
MODULE_DESCRIPTION("Qualcomm Technologies Inc ipq5018 pinctrl driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue
Block a user