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arm64: dts: qcom: x1e80100: Add gpu support

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Add the necessary dt nodes for gpu support in X1E80100.

Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240629015111.264564-6-quic_akhilpo@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Akhil P Oommen 2024-06-29 07:19:38 +05:30 committed by Bjorn Andersson
parent 9c99c33a90
commit 721e38301b
1 changed files with 195 additions and 0 deletions
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195
arch/arm64/boot/dts/qcom/x1e80100.dtsi
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@ -6,6 +6,7 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,x1e80100-dispcc.h>
#include <dt-bindings/clock/qcom,x1e80100-gcc.h>
#include <dt-bindings/clock/qcom,x1e80100-gpucc.h>
#include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/interconnect/qcom,icc.h>
@ -3131,6 +3132,200 @@
#reset-cells = <1>;
};
gpu: gpu@3d00000 {
compatible = "qcom,adreno-43050c01", "qcom,adreno";
reg = <0x0 0x03d00000 0x0 0x40000>,
<0x0 0x03d9e000 0x0 0x1000>,
<0x0 0x03d61000 0x0 0x800>;
reg-names = "kgsl_3d0_reg_memory",
"cx_mem",
"cx_dbgc";
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&adreno_smmu 0 0x0>,
<&adreno_smmu 1 0x0>;
operating-points-v2 = <&gpu_opp_table>;
qcom,gmu = <&gmu>;
#cooling-cells = <2>;
interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "gfx-mem";
zap-shader {
memory-region = <&gpu_microcode_mem>;
firmware-name = "qcom/gen70500_zap.mbn";
};
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-1100000000 {
opp-hz = /bits/ 64 <1100000000>;
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
opp-peak-kBps = <16500000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
opp-peak-kBps = <14398438>;
};
opp-925000000 {
opp-hz = /bits/ 64 <925000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
opp-peak-kBps = <14398438>;
};
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
opp-peak-kBps = <12449219>;
};
opp-744000000 {
opp-hz = /bits/ 64 <744000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
opp-peak-kBps = <10687500>;
};
opp-687000000 {
opp-hz = /bits/ 64 <687000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
opp-peak-kBps = <8171875>;
};
opp-550000000 {
opp-hz = /bits/ 64 <550000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
opp-peak-kBps = <6074219>;
};
opp-390000000 {
opp-hz = /bits/ 64 <390000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
opp-peak-kBps = <3000000>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
opp-peak-kBps = <2136719>;
};
};
};
gmu: gmu@3d6a000 {
compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu";
reg = <0x0 0x03d6a000 0x0 0x35000>,
<0x0 0x03d50000 0x0 0x10000>,
<0x0 0x0b280000 0x0 0x10000>;
reg-names = "gmu", "rscc", "gmu_pdc";
interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hfi", "gmu";
clocks = <&gpucc GPU_CC_AHB_CLK>,
<&gpucc GPU_CC_CX_GMU_CLK>,
<&gpucc GPU_CC_CXO_CLK>,
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
<&gpucc GPU_CC_HUB_CX_INT_CLK>,
<&gpucc GPU_CC_DEMET_CLK>;
clock-names = "ahb",
"gmu",
"cxo",
"axi",
"memnoc",
"hub",
"demet";
power-domains = <&gpucc GPU_CX_GDSC>,
<&gpucc GPU_GX_GDSC>;
power-domain-names = "cx",
"gx";
iommus = <&adreno_smmu 5 0x0>;
qcom,qmp = <&aoss_qmp>;
operating-points-v2 = <&gmu_opp_table>;
gmu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-550000000 {
opp-hz = /bits/ 64 <550000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
};
opp-220000000 {
opp-hz = /bits/ 64 <220000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
};
};
};
gpucc: clock-controller@3d90000 {
compatible = "qcom,x1e80100-gpucc";
reg = <0 0x03d90000 0 0xa000>;
clocks = <&bi_tcxo_div2>,
<&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
adreno_smmu: iommu@3da0000 {
compatible = "qcom,x1e80100-smmu-500", "qcom,adreno-smmu",
"qcom,smmu-500", "arm,mmu-500";
reg = <0x0 0x03da0000 0x0 0x40000>;
#iommu-cells = <2>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
<&gpucc GPU_CC_AHB_CLK>;
clock-names = "hlos",
"bus",
"iface",
"ahb";
power-domains = <&gpucc GPU_CX_GDSC>;
dma-coherent;
};
gem_noc: interconnect@26400000 {
compatible = "qcom,x1e80100-gem-noc";
reg = <0 0x26400000 0 0x311200>;