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drm/i915/skl: Extend WaDisableChickenBitTSGBarrierAckForFFSliceCS

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There is ambiguity in the documentation between D0 and E0.
Extend this workaround to E0.

References: BSID#779
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465309159-30531-23-git-send-email-mika.kuoppala@intel.com
This commit is contained in:
Mika Kuoppala 2016-06-07 17:19:14 +03:00 committed by Mika Kuoppala
parent 590e8ff04b
commit 71dce58c8e
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/i915/intel_ringbuffer.c
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@ -1085,7 +1085,7 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
_MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
}
if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0)) {
if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0)) {
/* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
I915_WRITE(FF_SLICE_CS_CHICKEN2,
_MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));