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[netdrvr] sh_eth: Add SH7619 support
Add support SH7619 Internal ethernet controler. Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
This commit is contained in:
Yoshinori Sato
Jeff Garzik
parent
d91d4bb9db
commit
71557a37ad
11
arch/sh/include/asm/sh_eth.h
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11
arch/sh/include/asm/sh_eth.h
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@ -0,0 +1,11 @@
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#ifndef __ASM_SH_ETH_H__
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#define __ASM_SH_ETH_H__
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enum {EDMAC_LITTLE_ENDIAN, EDMAC_BIG_ENDIAN};
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struct sh_eth_plat_data {
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int phy;
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int edmac_endian;
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};
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#endif
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@ -510,14 +510,15 @@ config STNIC
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config SH_ETH
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tristate "Renesas SuperH Ethernet support"
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depends on SUPERH && \
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(CPU_SUBTYPE_SH7710 || CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7763)
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(CPU_SUBTYPE_SH7710 || CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7763 || \
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CPU_SUBTYPE_SH7619)
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select CRC32
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select MII
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select MDIO_BITBANG
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select PHYLIB
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help
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Renesas SuperH Ethernet device driver.
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This driver support SH7710, SH7712 and SH7763.
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This driver support SH7710, SH7712, SH7763 and SH7619.
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config SUNLANCE
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tristate "Sun LANCE support"
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@ -34,6 +34,29 @@
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#include "sh_eth.h"
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/* CPU <-> EDMAC endian convert */
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static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
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{
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switch (mdp->edmac_endian) {
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case EDMAC_LITTLE_ENDIAN:
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return cpu_to_le32(x);
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case EDMAC_BIG_ENDIAN:
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return cpu_to_be32(x);
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}
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return x;
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}
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static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
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{
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switch (mdp->edmac_endian) {
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case EDMAC_LITTLE_ENDIAN:
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return le32_to_cpu(x);
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case EDMAC_BIG_ENDIAN:
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return be32_to_cpu(x);
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}
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return x;
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}
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/*
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* Program the hardware MAC address from dev->dev_addr.
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*/
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@ -240,7 +263,7 @@ static void sh_eth_ring_format(struct net_device *ndev)
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/* RX descriptor */
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rxdesc = &mdp->rx_ring[i];
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rxdesc->addr = (u32)skb->data & ~0x3UL;
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rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
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rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
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/* The size of the buffer is 16 byte boundary. */
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rxdesc->buffer_length = (mdp->rx_buf_sz + 16) & ~0x0F;
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@ -262,7 +285,7 @@ static void sh_eth_ring_format(struct net_device *ndev)
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mdp->dirty_rx = (u32) (i - RX_RING_SIZE);
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/* Mark the last entry as wrapping the ring. */
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rxdesc->status |= cpu_to_le32(RD_RDEL);
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rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
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memset(mdp->tx_ring, 0, tx_ringsize);
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@ -270,10 +293,10 @@ static void sh_eth_ring_format(struct net_device *ndev)
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for (i = 0; i < TX_RING_SIZE; i++) {
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mdp->tx_skbuff[i] = NULL;
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txdesc = &mdp->tx_ring[i];
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txdesc->status = cpu_to_le32(TD_TFP);
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txdesc->status = cpu_to_edmac(mdp, TD_TFP);
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txdesc->buffer_length = 0;
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if (i == 0) {
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/* Rx descriptor address set */
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/* Tx descriptor address set */
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ctrl_outl((u32)txdesc, ioaddr + TDLAR);
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#if defined(CONFIG_CPU_SUBTYPE_SH7763)
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ctrl_outl((u32)txdesc, ioaddr + TDFAR);
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@ -281,13 +304,13 @@ static void sh_eth_ring_format(struct net_device *ndev)
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}
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}
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/* Rx descriptor address set */
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/* Tx descriptor address set */
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#if defined(CONFIG_CPU_SUBTYPE_SH7763)
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ctrl_outl((u32)txdesc, ioaddr + TDFXR);
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ctrl_outl(0x1, ioaddr + TDFFR);
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#endif
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txdesc->status |= cpu_to_le32(TD_TDLE);
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txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
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}
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/* Get skb and descriptor buffer */
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@ -455,7 +478,7 @@ static int sh_eth_txfree(struct net_device *ndev)
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for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
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entry = mdp->dirty_tx % TX_RING_SIZE;
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txdesc = &mdp->tx_ring[entry];
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if (txdesc->status & cpu_to_le32(TD_TACT))
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if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
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break;
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/* Free the original skb. */
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if (mdp->tx_skbuff[entry]) {
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@ -463,9 +486,9 @@ static int sh_eth_txfree(struct net_device *ndev)
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mdp->tx_skbuff[entry] = NULL;
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freeNum++;
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}
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txdesc->status = cpu_to_le32(TD_TFP);
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txdesc->status = cpu_to_edmac(mdp, TD_TFP);
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if (entry >= TX_RING_SIZE - 1)
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txdesc->status |= cpu_to_le32(TD_TDLE);
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txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
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mdp->stats.tx_packets++;
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mdp->stats.tx_bytes += txdesc->buffer_length;
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@ -486,8 +509,8 @@ static int sh_eth_rx(struct net_device *ndev)
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u32 desc_status, reserve = 0;
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rxdesc = &mdp->rx_ring[entry];
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while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
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desc_status = le32_to_cpu(rxdesc->status);
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while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
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desc_status = edmac_to_cpu(mdp, rxdesc->status);
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pkt_len = rxdesc->frame_length;
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if (--boguscnt < 0)
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@ -522,7 +545,7 @@ static int sh_eth_rx(struct net_device *ndev)
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mdp->stats.rx_packets++;
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mdp->stats.rx_bytes += pkt_len;
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}
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rxdesc->status |= cpu_to_le32(RD_RACT);
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rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
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entry = (++mdp->cur_rx) % RX_RING_SIZE;
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}
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@ -552,10 +575,10 @@ static int sh_eth_rx(struct net_device *ndev)
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}
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if (entry >= RX_RING_SIZE - 1)
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rxdesc->status |=
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cpu_to_le32(RD_RACT | RD_RFP | RD_RDEL);
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cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
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else
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rxdesc->status |=
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cpu_to_le32(RD_RACT | RD_RFP);
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cpu_to_edmac(mdp, RD_RACT | RD_RFP);
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}
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/* Restart Rx engine if stopped. */
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@ -931,9 +954,9 @@ static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
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txdesc->buffer_length = skb->len;
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if (entry >= TX_RING_SIZE - 1)
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txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
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txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
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else
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txdesc->status |= cpu_to_le32(TD_TACT);
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txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
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mdp->cur_tx++;
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@ -1159,6 +1182,7 @@ static int sh_eth_drv_probe(struct platform_device *pdev)
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struct resource *res;
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struct net_device *ndev = NULL;
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struct sh_eth_private *mdp;
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struct sh_eth_plat_data *pd;
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/* get base addr */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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@ -1196,8 +1220,11 @@ static int sh_eth_drv_probe(struct platform_device *pdev)
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mdp = netdev_priv(ndev);
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spin_lock_init(&mdp->lock);
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pd = (struct sh_eth_plat_data *)(pdev->dev.platform_data);
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/* get PHY ID */
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mdp->phy_id = (int)pdev->dev.platform_data;
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mdp->phy_id = pd->phy;
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/* EDMAC endian */
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mdp->edmac_endian = pd->edmac_endian;
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/* set function */
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ndev->open = sh_eth_open;
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@ -1217,12 +1244,16 @@ static int sh_eth_drv_probe(struct platform_device *pdev)
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/* First device only init */
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if (!devno) {
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#if defined(ARSTR)
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/* reset device */
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ctrl_outl(ARSTR_ARSTR, ARSTR);
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mdelay(1);
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#endif
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#if defined(SH_TSU_ADDR)
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/* TSU init (Init only)*/
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sh_eth_tsu_init(SH_TSU_ADDR);
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#endif
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}
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/* network device register */
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@ -1240,8 +1271,8 @@ static int sh_eth_drv_probe(struct platform_device *pdev)
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ndev->name, CARDNAME, (u32) ndev->base_addr);
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for (i = 0; i < 5; i++)
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printk(KERN_INFO "%02X:", ndev->dev_addr[i]);
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printk(KERN_INFO "%02X, IRQ %d.\n", ndev->dev_addr[i], ndev->irq);
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printk("%02X:", ndev->dev_addr[i]);
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printk("%02X, IRQ %d.\n", ndev->dev_addr[i], ndev->irq);
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platform_set_drvdata(pdev, ndev);
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@ -30,6 +30,8 @@
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#include <linux/netdevice.h>
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#include <linux/phy.h>
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#include <asm/sh_eth.h>
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#define CARDNAME "sh-eth"
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#define TX_TIMEOUT (5*HZ)
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#define TX_RING_SIZE 64 /* Tx ring size */
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@ -143,10 +145,11 @@
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#else /* CONFIG_CPU_SUBTYPE_SH7763 */
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# define RX_OFFSET 2 /* skb offset */
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#ifndef CONFIG_CPU_SUBTYPE_SH7619
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/* Chip base address */
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# define SH_TSU_ADDR 0xA7000804
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# define ARSTR 0xA7000800
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#endif
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/* Chip Registers */
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/* E-DMAC */
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# define EDMR 0x0000
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@ -384,7 +387,11 @@ enum FCFTR_BIT {
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FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
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};
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#define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0)
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#ifndef CONFIG_CPU_SUBTYPE_SH7619
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#define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0)
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#else
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#define FIFO_F_D_RFD (FCFTR_RFD0)
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#endif
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/* Transfer descriptor bit */
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enum TD_STS_BIT {
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@ -414,8 +421,10 @@ enum FELIC_MODE_BIT {
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#ifdef CONFIG_CPU_SUBTYPE_SH7763
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#define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF |\
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ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
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#elif CONFIG_CPU_SUBTYPE_SH7619
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#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF)
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#else
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#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR ECMR_RXF | ECMR_TXF | ECMR_MCT)
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#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
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#endif
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/* ECSR */
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@ -485,7 +494,11 @@ enum RPADIR_BIT {
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/* FDR */
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enum FIFO_SIZE_BIT {
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#ifndef CONFIG_CPU_SUBTYPE_SH7619
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FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
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#else
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FIFO_SIZE_T = 0x00000100, FIFO_SIZE_R = 0x00000001,
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#endif
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};
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enum phy_offsets {
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PHY_CTRL = 0, PHY_STAT = 1, PHY_IDT1 = 2, PHY_IDT2 = 3,
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@ -601,7 +614,7 @@ struct sh_eth_txdesc {
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#endif
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u32 addr; /* TD2 */
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u32 pad1; /* padding data */
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};
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} __attribute__((aligned(2), packed));
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/*
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* The sh ether Rx buffer descriptors.
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@ -618,7 +631,7 @@ struct sh_eth_rxdesc {
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#endif
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u32 addr; /* RD2 */
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u32 pad0; /* padding data */
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};
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} __attribute__((aligned(2), packed));
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struct sh_eth_private {
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dma_addr_t rx_desc_dma;
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@ -633,6 +646,7 @@ struct sh_eth_private {
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u32 cur_rx, dirty_rx; /* Producer/consumer ring indices */
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u32 cur_tx, dirty_tx;
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u32 rx_buf_sz; /* Based on MTU+slack. */
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int edmac_endian;
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/* MII transceiver section. */
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u32 phy_id; /* PHY ID */
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struct mii_bus *mii_bus; /* MDIO bus control */
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