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drm/i915: Collect dbuf device info into a sub-struct
Collect the related dbuf information into a struct. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210416171011.19012-2-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
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@ -4777,7 +4777,7 @@ static void gen9_dbuf_slice_set(struct drm_i915_private *dev_priv,
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void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
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u8 req_slices)
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{
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int num_slices = INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
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int num_slices = INTEL_INFO(dev_priv)->dbuf.num_slices;
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struct i915_power_domains *power_domains = &dev_priv->power_domains;
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enum dbuf_slice slice;
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@ -4825,7 +4825,7 @@ static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
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static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
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{
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const int num_slices = INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
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int num_slices = INTEL_INFO(dev_priv)->dbuf.num_slices;
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enum dbuf_slice slice;
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for (slice = DBUF_S1; slice < (DBUF_S1 + num_slices); slice++)
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@ -647,8 +647,8 @@ static const struct intel_device_info chv_info = {
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.has_gt_uc = 1, \
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.display.has_hdcp = 1, \
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.display.has_ipc = 1, \
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.ddb_size = 896, \
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.num_supported_dbuf_slices = 1
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.dbuf.size = 896, \
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.dbuf.num_slices = 1
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#define SKL_PLATFORM \
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GEN9_FEATURES, \
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@ -683,7 +683,7 @@ static const struct intel_device_info skl_gt4_info = {
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#define GEN9_LP_FEATURES \
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GEN(9), \
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.is_lp = 1, \
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.num_supported_dbuf_slices = 1, \
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.dbuf.num_slices = 1, \
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.display.has_hotplug = 1, \
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.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
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.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
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@ -720,14 +720,14 @@ static const struct intel_device_info skl_gt4_info = {
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static const struct intel_device_info bxt_info = {
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GEN9_LP_FEATURES,
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PLATFORM(INTEL_BROXTON),
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.ddb_size = 512,
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.dbuf.size = 512,
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};
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static const struct intel_device_info glk_info = {
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GEN9_LP_FEATURES,
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PLATFORM(INTEL_GEMINILAKE),
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.display.ver = 10,
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.ddb_size = 1024,
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.dbuf.size = 1024,
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GLK_COLORS,
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};
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@ -790,7 +790,7 @@ static const struct intel_device_info cml_gt2_info = {
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#define GEN10_FEATURES \
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GEN9_FEATURES, \
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GEN(10), \
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.ddb_size = 1024, \
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.dbuf.size = 1024, \
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.display.has_dsc = 1, \
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.has_coherent_ggtt = false, \
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GLK_COLORS
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@ -830,8 +830,8 @@ static const struct intel_device_info cnl_info = {
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[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
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}, \
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GEN(11), \
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.ddb_size = 2048, \
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.num_supported_dbuf_slices = 2, \
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.dbuf.size = 2048, \
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.dbuf.num_slices = 2, \
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.has_logical_ring_elsq = 1, \
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.color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
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@ -196,8 +196,10 @@ struct intel_device_info {
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#undef DEFINE_FLAG
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} display;
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u16 ddb_size; /* in blocks */
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u8 num_supported_dbuf_slices; /* number of DBuf slices */
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struct {
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u16 size; /* in blocks */
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u8 num_slices;
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} dbuf;
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/* Register offsets for the various display pipes and transcoders */
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int pipe_offsets[I915_MAX_TRANSCODERS];
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@ -3637,10 +3637,10 @@ bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv)
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u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv)
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{
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int i;
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int max_slices = INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
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int num_slices = INTEL_INFO(dev_priv)->dbuf.num_slices;
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u8 enabled_slices_mask = 0;
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for (i = 0; i < max_slices; i++) {
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for (i = 0; i < num_slices; i++) {
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if (intel_uncore_read(&dev_priv->uncore, DBUF_CTL_S(i)) & DBUF_POWER_STATE)
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enabled_slices_mask |= BIT(i);
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}
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@ -4030,7 +4030,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
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static int intel_dbuf_size(struct drm_i915_private *dev_priv)
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{
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int ddb_size = INTEL_INFO(dev_priv)->ddb_size;
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int ddb_size = INTEL_INFO(dev_priv)->dbuf.size;
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drm_WARN_ON(&dev_priv->drm, ddb_size == 0);
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@ -4043,7 +4043,7 @@ static int intel_dbuf_size(struct drm_i915_private *dev_priv)
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static int intel_dbuf_slice_size(struct drm_i915_private *dev_priv)
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{
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return intel_dbuf_size(dev_priv) /
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INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
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INTEL_INFO(dev_priv)->dbuf.num_slices;
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}
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static void
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@ -4070,8 +4070,8 @@ u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv,
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{
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u32 slice_mask = 0;
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u16 ddb_size = intel_dbuf_size(dev_priv);
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u16 num_supported_slices = INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
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u16 slice_size = ddb_size / num_supported_slices;
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int num_slices = INTEL_INFO(dev_priv)->dbuf.num_slices;
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u16 slice_size = ddb_size / num_slices;
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u16 start_slice;
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u16 end_slice;
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@ -5828,7 +5828,7 @@ skl_compute_ddb(struct intel_atomic_state *state)
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"Enabled dbuf slices 0x%x -> 0x%x (out of %d dbuf slices)\n",
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old_dbuf_state->enabled_slices,
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new_dbuf_state->enabled_slices,
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INTEL_INFO(dev_priv)->num_supported_dbuf_slices);
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INTEL_INFO(dev_priv)->dbuf.num_slices);
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}
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for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
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