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PCI/AER: Remove HEST/FIRMWARE_FIRST parsing for AER ownership
Commit c100beb9cc ("PCI/AER: Use only _OSC to determine AER ownership")
removed the use of HEST in determining AER ownership, but the AER driver
still used HEST to verify AER ownership in some of its APIs.
Per the ACPI spec v6.3, sec 18.3.2.4, some HEST table entries contain a
FIRMWARE_FIRST bit, but that bit does not tell us anything about ownership
of the AER capability.
Remove parsing of HEST to look for FIRMWARE_FIRST.
Add pcie_aer_is_native() for the places that need to know whether the OS
owns the AER capability.
[bhelgaas: commit log, reorder patch, remove unused __aer_firmware_first]
Link: https://lore.kernel.org/r/9a37f53a4e6ff4942ff8e18dbb20b00e16c47341.1590534843.git.sathyanarayanan.kuppuswamy@linux.intel.com
Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
Kuppuswamy Sathyanarayanan
Bjorn Helgaas
parent
c100beb9cc
commit
708b200036
@ -217,118 +217,22 @@ void pcie_ecrc_get_policy(char *str)
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}
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#endif /* CONFIG_PCIE_ECRC */
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#ifdef CONFIG_ACPI_APEI
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static inline int hest_match_pci(struct acpi_hest_aer_common *p,
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struct pci_dev *pci)
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{
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return ACPI_HEST_SEGMENT(p->bus) == pci_domain_nr(pci->bus) &&
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ACPI_HEST_BUS(p->bus) == pci->bus->number &&
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p->device == PCI_SLOT(pci->devfn) &&
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p->function == PCI_FUNC(pci->devfn);
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}
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static inline bool hest_match_type(struct acpi_hest_header *hest_hdr,
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struct pci_dev *dev)
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{
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u16 hest_type = hest_hdr->type;
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u8 pcie_type = pci_pcie_type(dev);
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if ((hest_type == ACPI_HEST_TYPE_AER_ROOT_PORT &&
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pcie_type == PCI_EXP_TYPE_ROOT_PORT) ||
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(hest_type == ACPI_HEST_TYPE_AER_ENDPOINT &&
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pcie_type == PCI_EXP_TYPE_ENDPOINT) ||
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(hest_type == ACPI_HEST_TYPE_AER_BRIDGE &&
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(dev->class >> 16) == PCI_BASE_CLASS_BRIDGE))
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return true;
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return false;
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}
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struct aer_hest_parse_info {
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struct pci_dev *pci_dev;
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int firmware_first;
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};
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static int hest_source_is_pcie_aer(struct acpi_hest_header *hest_hdr)
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{
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if (hest_hdr->type == ACPI_HEST_TYPE_AER_ROOT_PORT ||
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hest_hdr->type == ACPI_HEST_TYPE_AER_ENDPOINT ||
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hest_hdr->type == ACPI_HEST_TYPE_AER_BRIDGE)
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return 1;
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return 0;
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}
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static int aer_hest_parse(struct acpi_hest_header *hest_hdr, void *data)
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{
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struct aer_hest_parse_info *info = data;
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struct acpi_hest_aer_common *p;
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int ff;
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if (!hest_source_is_pcie_aer(hest_hdr))
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return 0;
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p = (struct acpi_hest_aer_common *)(hest_hdr + 1);
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ff = !!(p->flags & ACPI_HEST_FIRMWARE_FIRST);
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/*
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* If no specific device is supplied, determine whether
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* FIRMWARE_FIRST is set for *any* PCIe device.
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*/
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if (!info->pci_dev) {
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info->firmware_first |= ff;
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return 0;
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}
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/* Otherwise, check the specific device */
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if (p->flags & ACPI_HEST_GLOBAL) {
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if (hest_match_type(hest_hdr, info->pci_dev))
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info->firmware_first = ff;
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} else
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if (hest_match_pci(p, info->pci_dev))
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info->firmware_first = ff;
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return 0;
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}
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static void aer_set_firmware_first(struct pci_dev *pci_dev)
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{
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int rc;
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struct aer_hest_parse_info info = {
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.pci_dev = pci_dev,
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.firmware_first = 0,
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};
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rc = apei_hest_parse(aer_hest_parse, &info);
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if (rc)
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pci_dev->__aer_firmware_first = 0;
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else
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pci_dev->__aer_firmware_first = info.firmware_first;
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pci_dev->__aer_firmware_first_valid = 1;
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}
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int pcie_aer_get_firmware_first(struct pci_dev *dev)
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{
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if (!pci_is_pcie(dev))
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return 0;
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if (pcie_ports_native)
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return 0;
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if (!dev->__aer_firmware_first_valid)
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aer_set_firmware_first(dev);
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return dev->__aer_firmware_first;
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}
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#endif
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#define PCI_EXP_AER_FLAGS (PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | \
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PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE)
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int pci_enable_pcie_error_reporting(struct pci_dev *dev)
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int pcie_aer_is_native(struct pci_dev *dev)
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{
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if (pcie_aer_get_firmware_first(dev))
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return -EIO;
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struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
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if (!dev->aer_cap)
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return 0;
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return pcie_ports_native || host->native_aer;
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}
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int pci_enable_pcie_error_reporting(struct pci_dev *dev)
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{
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if (!pcie_aer_is_native(dev))
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return -EIO;
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return pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_AER_FLAGS);
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@ -337,7 +241,7 @@ EXPORT_SYMBOL_GPL(pci_enable_pcie_error_reporting);
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int pci_disable_pcie_error_reporting(struct pci_dev *dev)
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{
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if (pcie_aer_get_firmware_first(dev))
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if (!pcie_aer_is_native(dev))
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return -EIO;
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return pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
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@ -362,7 +266,7 @@ int pci_aer_clear_nonfatal_status(struct pci_dev *dev)
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if (!pos)
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return -EIO;
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if (pcie_aer_get_firmware_first(dev))
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if (!pcie_aer_is_native(dev))
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return -EIO;
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/* Clear status bits for ERR_NONFATAL errors only */
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@ -385,7 +289,7 @@ void pci_aer_clear_fatal_status(struct pci_dev *dev)
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if (!pos)
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return;
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if (pcie_aer_get_firmware_first(dev))
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if (!pcie_aer_is_native(dev))
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return;
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/* Clear status bits for ERR_FATAL errors only */
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@ -435,7 +339,7 @@ int pci_aer_raw_clear_status(struct pci_dev *dev)
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int pci_aer_clear_status(struct pci_dev *dev)
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{
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if (pcie_aer_get_firmware_first(dev))
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if (!pcie_aer_is_native(dev))
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return -EIO;
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return pci_aer_raw_clear_status(dev);
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@ -284,7 +284,7 @@ static int dpc_probe(struct pcie_device *dev)
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int status;
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u16 ctl, cap;
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if (pcie_aer_get_firmware_first(pdev) && !pcie_ports_dpc_native)
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if (!pcie_aer_is_native(pdev) && !pcie_ports_dpc_native)
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return -ENOTSUPP;
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status = devm_request_threaded_irq(device, dev->irq, dpc_irq,
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@ -29,8 +29,10 @@ extern bool pcie_ports_dpc_native;
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#ifdef CONFIG_PCIEAER
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int pcie_aer_init(void);
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int pcie_aer_is_native(struct pci_dev *dev);
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#else
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static inline int pcie_aer_init(void) { return 0; }
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static inline int pcie_aer_is_native(struct pci_dev *dev) { return 0; }
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#endif
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#ifdef CONFIG_HOTPLUG_PCI_PCIE
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@ -147,16 +149,5 @@ static inline bool pcie_pme_no_msi(void) { return false; }
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static inline void pcie_pme_interrupt_enable(struct pci_dev *dev, bool en) {}
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#endif /* !CONFIG_PCIE_PME */
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#ifdef CONFIG_ACPI_APEI
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int pcie_aer_get_firmware_first(struct pci_dev *pci_dev);
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#else
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static inline int pcie_aer_get_firmware_first(struct pci_dev *pci_dev)
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{
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if (pci_dev->__aer_firmware_first_valid)
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return pci_dev->__aer_firmware_first;
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return 0;
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}
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#endif
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struct device *pcie_port_find_device(struct pci_dev *dev, u32 service);
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#endif /* _PORTDRV_H_ */
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@ -420,8 +420,6 @@ struct pci_dev {
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* mappings to make sure they cannot access arbitrary memory.
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*/
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unsigned int untrusted:1;
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unsigned int __aer_firmware_first_valid:1;
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unsigned int __aer_firmware_first:1;
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unsigned int broken_intx_masking:1; /* INTx masking can't be used */
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unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
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unsigned int irq_managed:1;
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