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drm/amdgpu: dynamic initialize ip offset for cyan_skillfish
Add ip offset definition for cyan_skillfish and initialize it. v2: squash in ip_offset updates (Alex) Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Tao Zhou
Alex Deucher
parent
d0f56dc25a
commit
708391977b
@ -76,7 +76,7 @@ amdgpu-y += \
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vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o \
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arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o vangogh_reg_init.o \
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nbio_v7_2.o dimgrey_cavefish_reg_init.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o \
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beige_goby_reg_init.o yellow_carp_reg_init.o
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beige_goby_reg_init.o yellow_carp_reg_init.o cyan_skillfish_reg_init.o
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# add DF block
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amdgpu-y += \
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51
drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c
Normal file
51
drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c
Normal file
@ -0,0 +1,51 @@
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/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#include "nv.h"
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#include "soc15_common.h"
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#include "soc15_hw_ip.h"
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#include "cyan_skillfish_ip_offset.h"
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int cyan_skillfish_reg_base_init(struct amdgpu_device *adev)
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{
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/* HW has more IP blocks, only initialized the blocke needed by driver */
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uint32_t i;
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for (i = 0 ; i < MAX_INSTANCE ; ++i) {
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adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
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adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
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adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
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adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
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adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
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adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
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adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
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adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(UVD0_BASE.instance[i]));
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adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
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adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DMU_BASE.instance[i]));
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adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
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adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
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adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
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adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
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}
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return 0;
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}
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@ -666,6 +666,9 @@ legacy_init:
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case CHIP_YELLOW_CARP:
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yellow_carp_reg_base_init(adev);
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break;
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case CHIP_CYAN_SKILLFISH:
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cyan_skillfish_reg_base_init(adev);
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break;
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default:
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return -EINVAL;
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}
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@ -38,5 +38,6 @@ void vangogh_reg_base_init(struct amdgpu_device *adev);
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int dimgrey_cavefish_reg_base_init(struct amdgpu_device *adev);
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int beige_goby_reg_base_init(struct amdgpu_device *adev);
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int yellow_carp_reg_base_init(struct amdgpu_device *adev);
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int cyan_skillfish_reg_base_init(struct amdgpu_device *adev);
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#endif
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714
drivers/gpu/drm/amd/include/cyan_skillfish_ip_offset.h
Normal file
714
drivers/gpu/drm/amd/include/cyan_skillfish_ip_offset.h
Normal file
@ -0,0 +1,714 @@
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/*
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* Copyright (C) 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
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* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _cyan_skillfish_ip_offset_HEADER
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#define _cyan_skillfish_ip_offset_HEADER
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#define MAX_INSTANCE 6
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#define MAX_SEGMENT 5
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struct IP_BASE_INSTANCE
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{
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unsigned int segment[MAX_SEGMENT];
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};
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struct IP_BASE
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{
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struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
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};
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static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C00, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } } } };
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static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0, 0, 0, 0 } },
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{ { 0x00016E00, 0, 0, 0, 0 } },
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{ { 0x00017000, 0, 0, 0, 0 } },
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{ { 0x00017200, 0, 0, 0, 0 } },
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{ { 0x00017E00, 0, 0, 0, 0 } },
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{ { 0x0001B000, 0, 0, 0, 0 } } } };
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static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } } } };
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static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } } } };
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static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } } } };
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static const struct IP_BASE GC_BASE ={ { { { 0x00001260, 0x0000A000, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } } } };
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static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } } } };
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static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } } } };
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static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } } } };
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static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } } } };
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static const struct IP_BASE NBIO_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } } } };
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static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } } } };
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static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } } } };
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static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } } } };
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static const struct IP_BASE UMC0_BASE ={ { { { 0x00014000, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } } } };
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static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0 } } } };
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#define ATHUB_BASE__INST0_SEG0 0x00000C00
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#define ATHUB_BASE__INST0_SEG1 0
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#define ATHUB_BASE__INST0_SEG2 0
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#define ATHUB_BASE__INST0_SEG3 0
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#define ATHUB_BASE__INST0_SEG4 0
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#define ATHUB_BASE__INST1_SEG0 0
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#define ATHUB_BASE__INST1_SEG1 0
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#define ATHUB_BASE__INST1_SEG2 0
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#define ATHUB_BASE__INST1_SEG3 0
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#define ATHUB_BASE__INST1_SEG4 0
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#define ATHUB_BASE__INST2_SEG0 0
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#define ATHUB_BASE__INST2_SEG1 0
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#define ATHUB_BASE__INST2_SEG2 0
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#define ATHUB_BASE__INST2_SEG3 0
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#define ATHUB_BASE__INST2_SEG4 0
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#define ATHUB_BASE__INST3_SEG0 0
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#define ATHUB_BASE__INST3_SEG1 0
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#define ATHUB_BASE__INST3_SEG2 0
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#define ATHUB_BASE__INST3_SEG3 0
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#define ATHUB_BASE__INST3_SEG4 0
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#define ATHUB_BASE__INST4_SEG0 0
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#define ATHUB_BASE__INST4_SEG1 0
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#define ATHUB_BASE__INST4_SEG2 0
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#define ATHUB_BASE__INST4_SEG3 0
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#define ATHUB_BASE__INST4_SEG4 0
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#define ATHUB_BASE__INST5_SEG0 0
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#define ATHUB_BASE__INST5_SEG1 0
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#define ATHUB_BASE__INST5_SEG2 0
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#define ATHUB_BASE__INST5_SEG3 0
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#define ATHUB_BASE__INST5_SEG4 0
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#define CLK_BASE__INST0_SEG0 0x00016C00
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#define CLK_BASE__INST0_SEG1 0
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#define CLK_BASE__INST0_SEG2 0
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#define CLK_BASE__INST0_SEG3 0
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#define CLK_BASE__INST0_SEG4 0
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#define CLK_BASE__INST1_SEG0 0x00016E00
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#define CLK_BASE__INST1_SEG1 0
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#define CLK_BASE__INST1_SEG2 0
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#define CLK_BASE__INST1_SEG3 0
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#define CLK_BASE__INST1_SEG4 0
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#define CLK_BASE__INST2_SEG0 0x00017000
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#define CLK_BASE__INST2_SEG1 0
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#define CLK_BASE__INST2_SEG2 0
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#define CLK_BASE__INST2_SEG3 0
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#define CLK_BASE__INST2_SEG4 0
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#define CLK_BASE__INST3_SEG0 0x00017200
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#define CLK_BASE__INST3_SEG1 0
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#define CLK_BASE__INST3_SEG2 0
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#define CLK_BASE__INST3_SEG3 0
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#define CLK_BASE__INST3_SEG4 0
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#define CLK_BASE__INST4_SEG0 0x00017E00
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#define CLK_BASE__INST4_SEG1 0
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#define CLK_BASE__INST4_SEG2 0
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#define CLK_BASE__INST4_SEG3 0
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#define CLK_BASE__INST4_SEG4 0
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#define CLK_BASE__INST5_SEG0 0x0001B000
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#define CLK_BASE__INST5_SEG1 0
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#define CLK_BASE__INST5_SEG2 0
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#define CLK_BASE__INST5_SEG3 0
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#define CLK_BASE__INST5_SEG4 0
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#define DF_BASE__INST0_SEG0 0x00007000
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#define DF_BASE__INST0_SEG1 0
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#define DF_BASE__INST0_SEG2 0
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#define DF_BASE__INST0_SEG3 0
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#define DF_BASE__INST0_SEG4 0
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#define DF_BASE__INST1_SEG0 0
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#define DF_BASE__INST1_SEG1 0
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#define DF_BASE__INST1_SEG2 0
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#define DF_BASE__INST1_SEG3 0
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#define DF_BASE__INST1_SEG4 0
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#define DF_BASE__INST2_SEG0 0
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#define DF_BASE__INST2_SEG1 0
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#define DF_BASE__INST2_SEG2 0
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#define DF_BASE__INST2_SEG3 0
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#define DF_BASE__INST2_SEG4 0
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#define DF_BASE__INST3_SEG0 0
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#define DF_BASE__INST3_SEG1 0
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#define DF_BASE__INST3_SEG2 0
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#define DF_BASE__INST3_SEG3 0
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#define DF_BASE__INST3_SEG4 0
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#define DF_BASE__INST4_SEG0 0
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#define DF_BASE__INST4_SEG1 0
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#define DF_BASE__INST4_SEG2 0
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#define DF_BASE__INST4_SEG3 0
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#define DF_BASE__INST4_SEG4 0
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#define DF_BASE__INST5_SEG0 0
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#define DF_BASE__INST5_SEG1 0
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#define DF_BASE__INST5_SEG2 0
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#define DF_BASE__INST5_SEG3 0
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#define DF_BASE__INST5_SEG4 0
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#define DMU_BASE__INST0_SEG0 0x00000012
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#define DMU_BASE__INST0_SEG1 0x000000C0
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#define DMU_BASE__INST0_SEG2 0x000034C0
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#define DMU_BASE__INST0_SEG3 0x00009000
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#define DMU_BASE__INST0_SEG4 0
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#define DMU_BASE__INST1_SEG0 0
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#define DMU_BASE__INST1_SEG1 0
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#define DMU_BASE__INST1_SEG2 0
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#define DMU_BASE__INST1_SEG3 0
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#define DMU_BASE__INST1_SEG4 0
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#define DMU_BASE__INST2_SEG0 0
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#define DMU_BASE__INST2_SEG1 0
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#define DMU_BASE__INST2_SEG2 0
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#define DMU_BASE__INST2_SEG3 0
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#define DMU_BASE__INST2_SEG4 0
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#define DMU_BASE__INST3_SEG0 0
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#define DMU_BASE__INST3_SEG1 0
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#define DMU_BASE__INST3_SEG2 0
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#define DMU_BASE__INST3_SEG3 0
|
||||
#define DMU_BASE__INST3_SEG4 0
|
||||
|
||||
#define DMU_BASE__INST4_SEG0 0
|
||||
#define DMU_BASE__INST4_SEG1 0
|
||||
#define DMU_BASE__INST4_SEG2 0
|
||||
#define DMU_BASE__INST4_SEG3 0
|
||||
#define DMU_BASE__INST4_SEG4 0
|
||||
|
||||
#define DMU_BASE__INST5_SEG0 0
|
||||
#define DMU_BASE__INST5_SEG1 0
|
||||
#define DMU_BASE__INST5_SEG2 0
|
||||
#define DMU_BASE__INST5_SEG3 0
|
||||
#define DMU_BASE__INST5_SEG4 0
|
||||
|
||||
#define FUSE_BASE__INST0_SEG0 0x00017400
|
||||
#define FUSE_BASE__INST0_SEG1 0
|
||||
#define FUSE_BASE__INST0_SEG2 0
|
||||
#define FUSE_BASE__INST0_SEG3 0
|
||||
#define FUSE_BASE__INST0_SEG4 0
|
||||
|
||||
#define FUSE_BASE__INST1_SEG0 0
|
||||
#define FUSE_BASE__INST1_SEG1 0
|
||||
#define FUSE_BASE__INST1_SEG2 0
|
||||
#define FUSE_BASE__INST1_SEG3 0
|
||||
#define FUSE_BASE__INST1_SEG4 0
|
||||
|
||||
#define FUSE_BASE__INST2_SEG0 0
|
||||
#define FUSE_BASE__INST2_SEG1 0
|
||||
#define FUSE_BASE__INST2_SEG2 0
|
||||
#define FUSE_BASE__INST2_SEG3 0
|
||||
#define FUSE_BASE__INST2_SEG4 0
|
||||
|
||||
#define FUSE_BASE__INST3_SEG0 0
|
||||
#define FUSE_BASE__INST3_SEG1 0
|
||||
#define FUSE_BASE__INST3_SEG2 0
|
||||
#define FUSE_BASE__INST3_SEG3 0
|
||||
#define FUSE_BASE__INST3_SEG4 0
|
||||
|
||||
#define FUSE_BASE__INST4_SEG0 0
|
||||
#define FUSE_BASE__INST4_SEG1 0
|
||||
#define FUSE_BASE__INST4_SEG2 0
|
||||
#define FUSE_BASE__INST4_SEG3 0
|
||||
#define FUSE_BASE__INST4_SEG4 0
|
||||
|
||||
#define FUSE_BASE__INST5_SEG0 0
|
||||
#define FUSE_BASE__INST5_SEG1 0
|
||||
#define FUSE_BASE__INST5_SEG2 0
|
||||
#define FUSE_BASE__INST5_SEG3 0
|
||||
#define FUSE_BASE__INST5_SEG4 0
|
||||
|
||||
#define GC_BASE__INST0_SEG0 0x00001260
|
||||
#define GC_BASE__INST0_SEG1 0x0000A000
|
||||
#define GC_BASE__INST0_SEG2 0
|
||||
#define GC_BASE__INST0_SEG3 0
|
||||
#define GC_BASE__INST0_SEG4 0
|
||||
|
||||
#define GC_BASE__INST1_SEG0 0
|
||||
#define GC_BASE__INST1_SEG1 0
|
||||
#define GC_BASE__INST1_SEG2 0
|
||||
#define GC_BASE__INST1_SEG3 0
|
||||
#define GC_BASE__INST1_SEG4 0
|
||||
|
||||
#define GC_BASE__INST2_SEG0 0
|
||||
#define GC_BASE__INST2_SEG1 0
|
||||
#define GC_BASE__INST2_SEG2 0
|
||||
#define GC_BASE__INST2_SEG3 0
|
||||
#define GC_BASE__INST2_SEG4 0
|
||||
|
||||
#define GC_BASE__INST3_SEG0 0
|
||||
#define GC_BASE__INST3_SEG1 0
|
||||
#define GC_BASE__INST3_SEG2 0
|
||||
#define GC_BASE__INST3_SEG3 0
|
||||
#define GC_BASE__INST3_SEG4 0
|
||||
|
||||
#define GC_BASE__INST4_SEG0 0
|
||||
#define GC_BASE__INST4_SEG1 0
|
||||
#define GC_BASE__INST4_SEG2 0
|
||||
#define GC_BASE__INST4_SEG3 0
|
||||
#define GC_BASE__INST4_SEG4 0
|
||||
|
||||
#define GC_BASE__INST5_SEG0 0
|
||||
#define GC_BASE__INST5_SEG1 0
|
||||
#define GC_BASE__INST5_SEG2 0
|
||||
#define GC_BASE__INST5_SEG3 0
|
||||
#define GC_BASE__INST5_SEG4 0
|
||||
|
||||
#define HDP_BASE__INST0_SEG0 0x00000F20
|
||||
#define HDP_BASE__INST0_SEG1 0
|
||||
#define HDP_BASE__INST0_SEG2 0
|
||||
#define HDP_BASE__INST0_SEG3 0
|
||||
#define HDP_BASE__INST0_SEG4 0
|
||||
|
||||
#define HDP_BASE__INST1_SEG0 0
|
||||
#define HDP_BASE__INST1_SEG1 0
|
||||
#define HDP_BASE__INST1_SEG2 0
|
||||
#define HDP_BASE__INST1_SEG3 0
|
||||
#define HDP_BASE__INST1_SEG4 0
|
||||
|
||||
#define HDP_BASE__INST2_SEG0 0
|
||||
#define HDP_BASE__INST2_SEG1 0
|
||||
#define HDP_BASE__INST2_SEG2 0
|
||||
#define HDP_BASE__INST2_SEG3 0
|
||||
#define HDP_BASE__INST2_SEG4 0
|
||||
|
||||
#define HDP_BASE__INST3_SEG0 0
|
||||
#define HDP_BASE__INST3_SEG1 0
|
||||
#define HDP_BASE__INST3_SEG2 0
|
||||
#define HDP_BASE__INST3_SEG3 0
|
||||
#define HDP_BASE__INST3_SEG4 0
|
||||
|
||||
#define HDP_BASE__INST4_SEG0 0
|
||||
#define HDP_BASE__INST4_SEG1 0
|
||||
#define HDP_BASE__INST4_SEG2 0
|
||||
#define HDP_BASE__INST4_SEG3 0
|
||||
#define HDP_BASE__INST4_SEG4 0
|
||||
|
||||
#define HDP_BASE__INST5_SEG0 0
|
||||
#define HDP_BASE__INST5_SEG1 0
|
||||
#define HDP_BASE__INST5_SEG2 0
|
||||
#define HDP_BASE__INST5_SEG3 0
|
||||
#define HDP_BASE__INST5_SEG4 0
|
||||
|
||||
#define MMHUB_BASE__INST0_SEG0 0x0001A000
|
||||
#define MMHUB_BASE__INST0_SEG1 0
|
||||
#define MMHUB_BASE__INST0_SEG2 0
|
||||
#define MMHUB_BASE__INST0_SEG3 0
|
||||
#define MMHUB_BASE__INST0_SEG4 0
|
||||
|
||||
#define MMHUB_BASE__INST1_SEG0 0
|
||||
#define MMHUB_BASE__INST1_SEG1 0
|
||||
#define MMHUB_BASE__INST1_SEG2 0
|
||||
#define MMHUB_BASE__INST1_SEG3 0
|
||||
#define MMHUB_BASE__INST1_SEG4 0
|
||||
|
||||
#define MMHUB_BASE__INST2_SEG0 0
|
||||
#define MMHUB_BASE__INST2_SEG1 0
|
||||
#define MMHUB_BASE__INST2_SEG2 0
|
||||
#define MMHUB_BASE__INST2_SEG3 0
|
||||
#define MMHUB_BASE__INST2_SEG4 0
|
||||
|
||||
#define MMHUB_BASE__INST3_SEG0 0
|
||||
#define MMHUB_BASE__INST3_SEG1 0
|
||||
#define MMHUB_BASE__INST3_SEG2 0
|
||||
#define MMHUB_BASE__INST3_SEG3 0
|
||||
#define MMHUB_BASE__INST3_SEG4 0
|
||||
|
||||
#define MMHUB_BASE__INST4_SEG0 0
|
||||
#define MMHUB_BASE__INST4_SEG1 0
|
||||
#define MMHUB_BASE__INST4_SEG2 0
|
||||
#define MMHUB_BASE__INST4_SEG3 0
|
||||
#define MMHUB_BASE__INST4_SEG4 0
|
||||
|
||||
#define MMHUB_BASE__INST5_SEG0 0
|
||||
#define MMHUB_BASE__INST5_SEG1 0
|
||||
#define MMHUB_BASE__INST5_SEG2 0
|
||||
#define MMHUB_BASE__INST5_SEG3 0
|
||||
#define MMHUB_BASE__INST5_SEG4 0
|
||||
|
||||
#define MP0_BASE__INST0_SEG0 0x00016000
|
||||
#define MP0_BASE__INST0_SEG1 0
|
||||
#define MP0_BASE__INST0_SEG2 0
|
||||
#define MP0_BASE__INST0_SEG3 0
|
||||
#define MP0_BASE__INST0_SEG4 0
|
||||
|
||||
#define MP0_BASE__INST1_SEG0 0
|
||||
#define MP0_BASE__INST1_SEG1 0
|
||||
#define MP0_BASE__INST1_SEG2 0
|
||||
#define MP0_BASE__INST1_SEG3 0
|
||||
#define MP0_BASE__INST1_SEG4 0
|
||||
|
||||
#define MP0_BASE__INST2_SEG0 0
|
||||
#define MP0_BASE__INST2_SEG1 0
|
||||
#define MP0_BASE__INST2_SEG2 0
|
||||
#define MP0_BASE__INST2_SEG3 0
|
||||
#define MP0_BASE__INST2_SEG4 0
|
||||
|
||||
#define MP0_BASE__INST3_SEG0 0
|
||||
#define MP0_BASE__INST3_SEG1 0
|
||||
#define MP0_BASE__INST3_SEG2 0
|
||||
#define MP0_BASE__INST3_SEG3 0
|
||||
#define MP0_BASE__INST3_SEG4 0
|
||||
|
||||
#define MP0_BASE__INST4_SEG0 0
|
||||
#define MP0_BASE__INST4_SEG1 0
|
||||
#define MP0_BASE__INST4_SEG2 0
|
||||
#define MP0_BASE__INST4_SEG3 0
|
||||
#define MP0_BASE__INST4_SEG4 0
|
||||
|
||||
#define MP0_BASE__INST5_SEG0 0
|
||||
#define MP0_BASE__INST5_SEG1 0
|
||||
#define MP0_BASE__INST5_SEG2 0
|
||||
#define MP0_BASE__INST5_SEG3 0
|
||||
#define MP0_BASE__INST5_SEG4 0
|
||||
|
||||
#define MP1_BASE__INST0_SEG0 0x00016000
|
||||
#define MP1_BASE__INST0_SEG1 0
|
||||
#define MP1_BASE__INST0_SEG2 0
|
||||
#define MP1_BASE__INST0_SEG3 0
|
||||
#define MP1_BASE__INST0_SEG4 0
|
||||
|
||||
#define MP1_BASE__INST1_SEG0 0
|
||||
#define MP1_BASE__INST1_SEG1 0
|
||||
#define MP1_BASE__INST1_SEG2 0
|
||||
#define MP1_BASE__INST1_SEG3 0
|
||||
#define MP1_BASE__INST1_SEG4 0
|
||||
|
||||
#define MP1_BASE__INST2_SEG0 0
|
||||
#define MP1_BASE__INST2_SEG1 0
|
||||
#define MP1_BASE__INST2_SEG2 0
|
||||
#define MP1_BASE__INST2_SEG3 0
|
||||
#define MP1_BASE__INST2_SEG4 0
|
||||
|
||||
#define MP1_BASE__INST3_SEG0 0
|
||||
#define MP1_BASE__INST3_SEG1 0
|
||||
#define MP1_BASE__INST3_SEG2 0
|
||||
#define MP1_BASE__INST3_SEG3 0
|
||||
#define MP1_BASE__INST3_SEG4 0
|
||||
|
||||
#define MP1_BASE__INST4_SEG0 0
|
||||
#define MP1_BASE__INST4_SEG1 0
|
||||
#define MP1_BASE__INST4_SEG2 0
|
||||
#define MP1_BASE__INST4_SEG3 0
|
||||
#define MP1_BASE__INST4_SEG4 0
|
||||
|
||||
#define MP1_BASE__INST5_SEG0 0
|
||||
#define MP1_BASE__INST5_SEG1 0
|
||||
#define MP1_BASE__INST5_SEG2 0
|
||||
#define MP1_BASE__INST5_SEG3 0
|
||||
#define MP1_BASE__INST5_SEG4 0
|
||||
|
||||
#define NBIO_BASE__INST0_SEG0 0x00000000
|
||||
#define NBIO_BASE__INST0_SEG1 0x00000014
|
||||
#define NBIO_BASE__INST0_SEG2 0x00000D20
|
||||
#define NBIO_BASE__INST0_SEG3 0x00010400
|
||||
#define NBIO_BASE__INST0_SEG4 0
|
||||
|
||||
#define NBIO_BASE__INST1_SEG0 0
|
||||
#define NBIO_BASE__INST1_SEG1 0
|
||||
#define NBIO_BASE__INST1_SEG2 0
|
||||
#define NBIO_BASE__INST1_SEG3 0
|
||||
#define NBIO_BASE__INST1_SEG4 0
|
||||
|
||||
#define NBIO_BASE__INST2_SEG0 0
|
||||
#define NBIO_BASE__INST2_SEG1 0
|
||||
#define NBIO_BASE__INST2_SEG2 0
|
||||
#define NBIO_BASE__INST2_SEG3 0
|
||||
#define NBIO_BASE__INST2_SEG4 0
|
||||
|
||||
#define NBIO_BASE__INST3_SEG0 0
|
||||
#define NBIO_BASE__INST3_SEG1 0
|
||||
#define NBIO_BASE__INST3_SEG2 0
|
||||
#define NBIO_BASE__INST3_SEG3 0
|
||||
#define NBIO_BASE__INST3_SEG4 0
|
||||
|
||||
#define NBIO_BASE__INST4_SEG0 0
|
||||
#define NBIO_BASE__INST4_SEG1 0
|
||||
#define NBIO_BASE__INST4_SEG2 0
|
||||
#define NBIO_BASE__INST4_SEG3 0
|
||||
#define NBIO_BASE__INST4_SEG4 0
|
||||
|
||||
#define NBIO_BASE__INST5_SEG0 0
|
||||
#define NBIO_BASE__INST5_SEG1 0
|
||||
#define NBIO_BASE__INST5_SEG2 0
|
||||
#define NBIO_BASE__INST5_SEG3 0
|
||||
#define NBIO_BASE__INST5_SEG4 0
|
||||
|
||||
#define OSSSYS_BASE__INST0_SEG0 0x000010A0
|
||||
#define OSSSYS_BASE__INST0_SEG1 0
|
||||
#define OSSSYS_BASE__INST0_SEG2 0
|
||||
#define OSSSYS_BASE__INST0_SEG3 0
|
||||
#define OSSSYS_BASE__INST0_SEG4 0
|
||||
|
||||
#define OSSSYS_BASE__INST1_SEG0 0
|
||||
#define OSSSYS_BASE__INST1_SEG1 0
|
||||
#define OSSSYS_BASE__INST1_SEG2 0
|
||||
#define OSSSYS_BASE__INST1_SEG3 0
|
||||
#define OSSSYS_BASE__INST1_SEG4 0
|
||||
|
||||
#define OSSSYS_BASE__INST2_SEG0 0
|
||||
#define OSSSYS_BASE__INST2_SEG1 0
|
||||
#define OSSSYS_BASE__INST2_SEG2 0
|
||||
#define OSSSYS_BASE__INST2_SEG3 0
|
||||
#define OSSSYS_BASE__INST2_SEG4 0
|
||||
|
||||
#define OSSSYS_BASE__INST3_SEG0 0
|
||||
#define OSSSYS_BASE__INST3_SEG1 0
|
||||
#define OSSSYS_BASE__INST3_SEG2 0
|
||||
#define OSSSYS_BASE__INST3_SEG3 0
|
||||
#define OSSSYS_BASE__INST3_SEG4 0
|
||||
|
||||
#define OSSSYS_BASE__INST4_SEG0 0
|
||||
#define OSSSYS_BASE__INST4_SEG1 0
|
||||
#define OSSSYS_BASE__INST4_SEG2 0
|
||||
#define OSSSYS_BASE__INST4_SEG3 0
|
||||
#define OSSSYS_BASE__INST4_SEG4 0
|
||||
|
||||
#define OSSSYS_BASE__INST5_SEG0 0
|
||||
#define OSSSYS_BASE__INST5_SEG1 0
|
||||
#define OSSSYS_BASE__INST5_SEG2 0
|
||||
#define OSSSYS_BASE__INST5_SEG3 0
|
||||
#define OSSSYS_BASE__INST5_SEG4 0
|
||||
|
||||
#define SMUIO_BASE__INST0_SEG0 0x00016800
|
||||
#define SMUIO_BASE__INST0_SEG1 0x00016A00
|
||||
#define SMUIO_BASE__INST0_SEG2 0
|
||||
#define SMUIO_BASE__INST0_SEG3 0
|
||||
#define SMUIO_BASE__INST0_SEG4 0
|
||||
|
||||
#define SMUIO_BASE__INST1_SEG0 0
|
||||
#define SMUIO_BASE__INST1_SEG1 0
|
||||
#define SMUIO_BASE__INST1_SEG2 0
|
||||
#define SMUIO_BASE__INST1_SEG3 0
|
||||
#define SMUIO_BASE__INST1_SEG4 0
|
||||
|
||||
#define SMUIO_BASE__INST2_SEG0 0
|
||||
#define SMUIO_BASE__INST2_SEG1 0
|
||||
#define SMUIO_BASE__INST2_SEG2 0
|
||||
#define SMUIO_BASE__INST2_SEG3 0
|
||||
#define SMUIO_BASE__INST2_SEG4 0
|
||||
|
||||
#define SMUIO_BASE__INST3_SEG0 0
|
||||
#define SMUIO_BASE__INST3_SEG1 0
|
||||
#define SMUIO_BASE__INST3_SEG2 0
|
||||
#define SMUIO_BASE__INST3_SEG3 0
|
||||
#define SMUIO_BASE__INST3_SEG4 0
|
||||
|
||||
#define SMUIO_BASE__INST4_SEG0 0
|
||||
#define SMUIO_BASE__INST4_SEG1 0
|
||||
#define SMUIO_BASE__INST4_SEG2 0
|
||||
#define SMUIO_BASE__INST4_SEG3 0
|
||||
#define SMUIO_BASE__INST4_SEG4 0
|
||||
|
||||
#define SMUIO_BASE__INST5_SEG0 0
|
||||
#define SMUIO_BASE__INST5_SEG1 0
|
||||
#define SMUIO_BASE__INST5_SEG2 0
|
||||
#define SMUIO_BASE__INST5_SEG3 0
|
||||
#define SMUIO_BASE__INST5_SEG4 0
|
||||
|
||||
#define THM_BASE__INST0_SEG0 0x00016600
|
||||
#define THM_BASE__INST0_SEG1 0
|
||||
#define THM_BASE__INST0_SEG2 0
|
||||
#define THM_BASE__INST0_SEG3 0
|
||||
#define THM_BASE__INST0_SEG4 0
|
||||
|
||||
#define THM_BASE__INST1_SEG0 0
|
||||
#define THM_BASE__INST1_SEG1 0
|
||||
#define THM_BASE__INST1_SEG2 0
|
||||
#define THM_BASE__INST1_SEG3 0
|
||||
#define THM_BASE__INST1_SEG4 0
|
||||
|
||||
#define THM_BASE__INST2_SEG0 0
|
||||
#define THM_BASE__INST2_SEG1 0
|
||||
#define THM_BASE__INST2_SEG2 0
|
||||
#define THM_BASE__INST2_SEG3 0
|
||||
#define THM_BASE__INST2_SEG4 0
|
||||
|
||||
#define THM_BASE__INST3_SEG0 0
|
||||
#define THM_BASE__INST3_SEG1 0
|
||||
#define THM_BASE__INST3_SEG2 0
|
||||
#define THM_BASE__INST3_SEG3 0
|
||||
#define THM_BASE__INST3_SEG4 0
|
||||
|
||||
#define THM_BASE__INST4_SEG0 0
|
||||
#define THM_BASE__INST4_SEG1 0
|
||||
#define THM_BASE__INST4_SEG2 0
|
||||
#define THM_BASE__INST4_SEG3 0
|
||||
#define THM_BASE__INST4_SEG4 0
|
||||
|
||||
#define THM_BASE__INST5_SEG0 0
|
||||
#define THM_BASE__INST5_SEG1 0
|
||||
#define THM_BASE__INST5_SEG2 0
|
||||
#define THM_BASE__INST5_SEG3 0
|
||||
#define THM_BASE__INST5_SEG4 0
|
||||
|
||||
#define UMC0_BASE__INST0_SEG0 0x00014000
|
||||
#define UMC0_BASE__INST0_SEG1 0
|
||||
#define UMC0_BASE__INST0_SEG2 0
|
||||
#define UMC0_BASE__INST0_SEG3 0
|
||||
#define UMC0_BASE__INST0_SEG4 0
|
||||
|
||||
#define UMC0_BASE__INST1_SEG0 0
|
||||
#define UMC0_BASE__INST1_SEG1 0
|
||||
#define UMC0_BASE__INST1_SEG2 0
|
||||
#define UMC0_BASE__INST1_SEG3 0
|
||||
#define UMC0_BASE__INST1_SEG4 0
|
||||
|
||||
#define UMC0_BASE__INST2_SEG0 0
|
||||
#define UMC0_BASE__INST2_SEG1 0
|
||||
#define UMC0_BASE__INST2_SEG2 0
|
||||
#define UMC0_BASE__INST2_SEG3 0
|
||||
#define UMC0_BASE__INST2_SEG4 0
|
||||
|
||||
#define UMC0_BASE__INST3_SEG0 0
|
||||
#define UMC0_BASE__INST3_SEG1 0
|
||||
#define UMC0_BASE__INST3_SEG2 0
|
||||
#define UMC0_BASE__INST3_SEG3 0
|
||||
#define UMC0_BASE__INST3_SEG4 0
|
||||
|
||||
#define UMC0_BASE__INST4_SEG0 0
|
||||
#define UMC0_BASE__INST4_SEG1 0
|
||||
#define UMC0_BASE__INST4_SEG2 0
|
||||
#define UMC0_BASE__INST4_SEG3 0
|
||||
#define UMC0_BASE__INST4_SEG4 0
|
||||
|
||||
#define UMC0_BASE__INST5_SEG0 0
|
||||
#define UMC0_BASE__INST5_SEG1 0
|
||||
#define UMC0_BASE__INST5_SEG2 0
|
||||
#define UMC0_BASE__INST5_SEG3 0
|
||||
#define UMC0_BASE__INST5_SEG4 0
|
||||
|
||||
#define UVD0_BASE__INST0_SEG0 0x00007800
|
||||
#define UVD0_BASE__INST0_SEG1 0x00007E00
|
||||
#define UVD0_BASE__INST0_SEG2 0
|
||||
#define UVD0_BASE__INST0_SEG3 0
|
||||
#define UVD0_BASE__INST0_SEG4 0
|
||||
|
||||
#define UVD0_BASE__INST1_SEG0 0
|
||||
#define UVD0_BASE__INST1_SEG1 0
|
||||
#define UVD0_BASE__INST1_SEG2 0
|
||||
#define UVD0_BASE__INST1_SEG3 0
|
||||
#define UVD0_BASE__INST1_SEG4 0
|
||||
|
||||
#define UVD0_BASE__INST2_SEG0 0
|
||||
#define UVD0_BASE__INST2_SEG1 0
|
||||
#define UVD0_BASE__INST2_SEG2 0
|
||||
#define UVD0_BASE__INST2_SEG3 0
|
||||
#define UVD0_BASE__INST2_SEG4 0
|
||||
|
||||
#define UVD0_BASE__INST3_SEG0 0
|
||||
#define UVD0_BASE__INST3_SEG1 0
|
||||
#define UVD0_BASE__INST3_SEG2 0
|
||||
#define UVD0_BASE__INST3_SEG3 0
|
||||
#define UVD0_BASE__INST3_SEG4 0
|
||||
|
||||
#define UVD0_BASE__INST4_SEG0 0
|
||||
#define UVD0_BASE__INST4_SEG1 0
|
||||
#define UVD0_BASE__INST4_SEG2 0
|
||||
#define UVD0_BASE__INST4_SEG3 0
|
||||
#define UVD0_BASE__INST4_SEG4 0
|
||||
|
||||
#define UVD0_BASE__INST5_SEG0 0
|
||||
#define UVD0_BASE__INST5_SEG1 0
|
||||
#define UVD0_BASE__INST5_SEG2 0
|
||||
#define UVD0_BASE__INST5_SEG3 0
|
||||
#define UVD0_BASE__INST5_SEG4 0
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user