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octeontx2-af: Perform cpt lf teardown in non FLR path
Perform CPT LF teardown in non FLR path as well via cpt_lf_free() Currently CPT LF teardown and reset sequence is only done when FLR is handled with CPT LF still attached. This patch also fixes cpt_lf_alloc() to set EXEC_LDWB in CPT_AF_LFX_CTL2 when being completely overwritten as that is the default value and is better for performance. Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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4826090719
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7054d39ccf
@ -2532,7 +2532,8 @@ static void rvu_blklf_teardown(struct rvu *rvu, u16 pcifunc, u8 blkaddr)
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rvu_npa_lf_teardown(rvu, pcifunc, lf);
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else if ((block->addr == BLKADDR_CPT0) ||
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(block->addr == BLKADDR_CPT1))
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rvu_cpt_lf_teardown(rvu, pcifunc, lf, slot);
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rvu_cpt_lf_teardown(rvu, pcifunc, block->addr, lf,
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slot);
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err = rvu_lf_reset(rvu, block, lf);
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if (err) {
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@ -815,7 +815,8 @@ bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam, int blkaddr,
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/* CPT APIs */
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int rvu_cpt_register_interrupts(struct rvu *rvu);
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void rvu_cpt_unregister_interrupts(struct rvu *rvu);
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int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int lf, int slot);
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int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int lf,
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int slot);
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/* CN10K RVU */
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int rvu_set_channels_base(struct rvu *rvu);
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@ -377,9 +377,13 @@ int rvu_mbox_handler_cpt_lf_alloc(struct rvu *rvu,
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rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf), val);
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/* Set CPT LF NIX_PF_FUNC and SSO_PF_FUNC */
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val = (u64)req->nix_pf_func << 48 |
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(u64)req->sso_pf_func << 32;
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/* Set CPT LF NIX_PF_FUNC and SSO_PF_FUNC. EXE_LDWB is set
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* on reset.
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*/
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val = rvu_read64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf));
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val &= ~(GENMASK_ULL(63, 48) | GENMASK_ULL(47, 32));
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val |= ((u64)req->nix_pf_func << 48 |
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(u64)req->sso_pf_func << 32);
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rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf), val);
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}
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@ -389,7 +393,7 @@ int rvu_mbox_handler_cpt_lf_alloc(struct rvu *rvu,
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static int cpt_lf_free(struct rvu *rvu, struct msg_req *req, int blkaddr)
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{
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u16 pcifunc = req->hdr.pcifunc;
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int num_lfs, cptlf, slot;
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int num_lfs, cptlf, slot, err;
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struct rvu_block *block;
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block = &rvu->hw->block[blkaddr];
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@ -403,10 +407,15 @@ static int cpt_lf_free(struct rvu *rvu, struct msg_req *req, int blkaddr)
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if (cptlf < 0)
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return CPT_AF_ERR_LF_INVALID;
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/* Reset CPT LF group and priority */
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rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf), 0x0);
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/* Reset CPT LF NIX_PF_FUNC and SSO_PF_FUNC */
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rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf), 0x0);
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/* Perform teardown */
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rvu_cpt_lf_teardown(rvu, pcifunc, blkaddr, cptlf, slot);
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/* Reset LF */
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err = rvu_lf_reset(rvu, block, cptlf);
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if (err) {
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dev_err(rvu->dev, "Failed to reset blkaddr %d LF%d\n",
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block->addr, cptlf);
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}
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}
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return 0;
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@ -850,15 +859,10 @@ static void cpt_lf_disable_iqueue(struct rvu *rvu, int blkaddr, int slot)
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dev_warn(rvu->dev, "CPT FLR hits hard loop counter\n");
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}
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int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int lf, int slot)
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int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int lf, int slot)
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{
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int blkaddr;
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u64 reg;
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blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_CPT, pcifunc);
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if (blkaddr != BLKADDR_CPT0 && blkaddr != BLKADDR_CPT1)
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return -EINVAL;
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/* Enable BAR2 ALIAS for this pcifunc. */
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reg = BIT_ULL(16) | pcifunc;
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rvu_write64(rvu, blkaddr, CPT_AF_BAR2_SEL, reg);
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