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ucc_geth: NAPI-related bug fixes
Based partly on the gianfar driver, this patch fixes several bugs which were causing NAPI to be completely unusable. * An IRQ is still needed in NAPI, to kick off NAPI task, and for Tx processing. Request the IRQ. * If rx_work_limit = 0 we are not complete. * While running Rx NAPI processing we must mask Rx events, including Rx busy. * ucc_geth_rx function does not need a lock. Could lead to deadlock in NAPI case. * There's no need to loop reading ucce multiple times in the ISR, so while adding the call to schedule NAPI which was not there, simplify the event processing into if-else format. * Rx Busy now kicks off NAPI processing, while still being counted as an error. Signed-off-by: Michael Reiss <michael.f.reiss@freescale.com> Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Michael Reiss
Jeff Garzik
parent
728de4c927
commit
702ff12ce7
@ -3416,7 +3416,6 @@ static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit
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ugeth_vdbg("%s: IN", __FUNCTION__);
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spin_lock(&ugeth->lock);
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/* collect received buffers */
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bd = ugeth->rxBd[rxQ];
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@ -3464,7 +3463,6 @@ static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit
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skb = get_new_skb(ugeth, bd);
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if (!skb) {
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ugeth_warn("%s: No Rx Data Buffer", __FUNCTION__);
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spin_unlock(&ugeth->lock);
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ugeth->stats.rx_dropped++;
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break;
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}
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@ -3485,7 +3483,6 @@ static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit
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}
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ugeth->rxBd[rxQ] = bd;
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spin_unlock(&ugeth->lock);
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return howmany;
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}
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@ -3537,23 +3534,38 @@ static int ucc_geth_tx(struct net_device *dev, u8 txQ)
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static int ucc_geth_poll(struct net_device *dev, int *budget)
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{
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struct ucc_geth_private *ugeth = netdev_priv(dev);
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struct ucc_geth_info *ug_info;
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struct ucc_fast_private *uccf;
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int howmany;
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int rx_work_limit = *budget;
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u8 rxQ = 0;
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u8 i;
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int rx_work_limit;
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register u32 uccm;
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ug_info = ugeth->ug_info;
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rx_work_limit = *budget;
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if (rx_work_limit > dev->quota)
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rx_work_limit = dev->quota;
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howmany = ucc_geth_rx(ugeth, rxQ, rx_work_limit);
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howmany = 0;
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for (i = 0; i < ug_info->numQueuesRx; i++) {
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howmany += ucc_geth_rx(ugeth, i, rx_work_limit);
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}
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dev->quota -= howmany;
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rx_work_limit -= howmany;
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*budget -= howmany;
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if (rx_work_limit >= 0)
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if (rx_work_limit > 0) {
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netif_rx_complete(dev);
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uccf = ugeth->uccf;
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uccm = in_be32(uccf->p_uccm);
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uccm |= UCCE_RX_EVENTS;
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out_be32(uccf->p_uccm, uccm);
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}
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return (rx_work_limit < 0) ? 1 : 0;
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return (rx_work_limit > 0) ? 0 : 1;
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}
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#endif /* CONFIG_UGETH_NAPI */
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@ -3563,10 +3575,13 @@ static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
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struct ucc_geth_private *ugeth = netdev_priv(dev);
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struct ucc_fast_private *uccf;
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struct ucc_geth_info *ug_info;
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register u32 ucce = 0;
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register u32 bit_mask = UCCE_RXBF_SINGLE_MASK;
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register u32 tx_mask = UCCE_TXBF_SINGLE_MASK;
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register u8 i;
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register u32 ucce;
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register u32 uccm;
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#ifndef CONFIG_UGETH_NAPI
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register u32 rx_mask;
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#endif
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register u32 tx_mask;
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u8 i;
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ugeth_vdbg("%s: IN", __FUNCTION__);
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@ -3576,48 +3591,53 @@ static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
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uccf = ugeth->uccf;
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ug_info = ugeth->ug_info;
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do {
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ucce |= (u32) (in_be32(uccf->p_ucce) & in_be32(uccf->p_uccm));
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/* read and clear events */
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ucce = (u32) in_be32(uccf->p_ucce);
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uccm = (u32) in_be32(uccf->p_uccm);
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ucce &= uccm;
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out_be32(uccf->p_ucce, ucce);
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/* clear event bits for next time */
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/* Side effect here is to mask ucce variable
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for future processing below. */
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out_be32(uccf->p_ucce, ucce); /* Clear with ones,
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but only bits in UCCM */
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/* We ignore Tx interrupts because Tx confirmation is
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done inside Tx routine */
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for (i = 0; i < ug_info->numQueuesRx; i++) {
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if (ucce & bit_mask)
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ucc_geth_rx(ugeth, i,
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(int)ugeth->ug_info->
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bdRingLenRx[i]);
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ucce &= ~bit_mask;
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bit_mask <<= 1;
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/* check for receive events that require processing */
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if (ucce & UCCE_RX_EVENTS) {
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#ifdef CONFIG_UGETH_NAPI
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if (netif_rx_schedule_prep(dev)) {
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uccm &= ~UCCE_RX_EVENTS;
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out_be32(uccf->p_uccm, uccm);
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__netif_rx_schedule(dev);
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}
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#else
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rx_mask = UCCE_RXBF_SINGLE_MASK;
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for (i = 0; i < ug_info->numQueuesRx; i++) {
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if (ucce & rx_mask)
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ucc_geth_rx(ugeth, i, (int)ugeth->ug_info->bdRingLenRx[i]);
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ucce &= ~rx_mask;
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rx_mask <<= 1;
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}
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#endif /* CONFIG_UGETH_NAPI */
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}
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/* Tx event processing */
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if (ucce & UCCE_TX_EVENTS) {
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spin_lock(&ugeth->lock);
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tx_mask = UCCE_TXBF_SINGLE_MASK;
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for (i = 0; i < ug_info->numQueuesTx; i++) {
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if (ucce & tx_mask)
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ucc_geth_tx(dev, i);
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ucce &= ~tx_mask;
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tx_mask <<= 1;
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}
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spin_unlock(&ugeth->lock);
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}
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/* Exceptions */
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/* Errors and other events */
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if (ucce & UCCE_OTHER) {
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if (ucce & UCCE_BSY) {
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ugeth_vdbg("Got BUSY irq!!!!");
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ugeth->stats.rx_errors++;
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ucce &= ~UCCE_BSY;
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}
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if (ucce & UCCE_OTHER) {
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ugeth_vdbg("Got frame with error (ucce - 0x%08x)!!!!",
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ucce);
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ugeth->stats.rx_errors++;
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ucce &= ~ucce;
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if (ucce & UCCE_TXE) {
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ugeth->stats.tx_errors++;
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}
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}
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while (ucce);
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return IRQ_HANDLED;
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}
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@ -3677,7 +3697,6 @@ static int ucc_geth_open(struct net_device *dev)
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phy_start(ugeth->phydev);
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#ifndef CONFIG_UGETH_NAPI
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err =
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request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler, 0,
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"UCC Geth", dev);
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@ -3687,7 +3706,6 @@ static int ucc_geth_open(struct net_device *dev)
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ucc_geth_stop(ugeth);
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return err;
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}
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#endif /* CONFIG_UGETH_NAPI */
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err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
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if (err) {
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@ -205,6 +205,9 @@ struct ucc_geth {
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#define UCCE_OTHER (UCCE_SCAR | UCCE_GRA | UCCE_CBPR | UCCE_BSY |\
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UCCE_RXC | UCCE_TXC | UCCE_TXE)
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#define UCCE_RX_EVENTS (UCCE_RXF | UCCE_BSY)
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#define UCCE_TX_EVENTS (UCCE_TXB | UCCE_TXE)
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/* UCC GETH UPSMR (Protocol Specific Mode Register) */
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#define UPSMR_ECM 0x04000000 /* Enable CAM
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Miss or
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