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r8169: support RTL8111E-VL.
Signed-off-by: Hayes Wang <hayeswang@realtek.com> Acked-by: Francois Romieu <romieu@fr.zoreil.com>
This commit is contained in:
Hayes Wang
Francois Romieu
parent
133ac40ac2
commit
70090424e5
@ -41,6 +41,7 @@
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#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
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#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
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#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
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#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
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#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
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#ifdef RTL8169_DEBUG
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@ -131,6 +132,7 @@ enum mac_version {
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RTL_GIGA_MAC_VER_31,
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RTL_GIGA_MAC_VER_32,
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RTL_GIGA_MAC_VER_33,
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RTL_GIGA_MAC_VER_34,
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RTL_GIGA_MAC_NONE = 0xff,
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};
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@ -214,7 +216,9 @@ static const struct {
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[RTL_GIGA_MAC_VER_32] =
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_R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1),
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[RTL_GIGA_MAC_VER_33] =
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_R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2)
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_R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2),
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[RTL_GIGA_MAC_VER_34] =
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_R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3)
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};
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#undef _R
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@ -1151,6 +1155,39 @@ static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
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rtl_writephy(tp, MII_BMCR, val & 0xffff);
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}
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static void rtl_link_chg_patch(struct rtl8169_private *tp)
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{
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void __iomem *ioaddr = tp->mmio_addr;
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struct net_device *dev = tp->dev;
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if (!netif_running(dev))
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return;
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if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
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if (RTL_R8(PHYstatus) & _1000bpsF) {
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rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
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0x00000011, ERIAR_EXGMAC);
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rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
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0x00000005, ERIAR_EXGMAC);
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} else if (RTL_R8(PHYstatus) & _100bps) {
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rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
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0x0000001f, ERIAR_EXGMAC);
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rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
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0x00000005, ERIAR_EXGMAC);
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} else {
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rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
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0x0000001f, ERIAR_EXGMAC);
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rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
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0x0000003f, ERIAR_EXGMAC);
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}
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/* Reset packet filter */
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rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
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ERIAR_EXGMAC);
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rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
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ERIAR_EXGMAC);
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}
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}
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static void __rtl8169_check_link_status(struct net_device *dev,
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struct rtl8169_private *tp,
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void __iomem *ioaddr, bool pm)
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@ -1159,6 +1196,7 @@ static void __rtl8169_check_link_status(struct net_device *dev,
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spin_lock_irqsave(&tp->lock, flags);
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if (tp->link_ok(ioaddr)) {
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rtl_link_chg_patch(tp);
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/* This is to cancel a scheduled suspend if there's one. */
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if (pm)
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pm_request_resume(&tp->pci_dev->dev);
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@ -1687,6 +1725,7 @@ static void rtl8169_get_mac_version(struct rtl8169_private *tp,
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int mac_version;
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} mac_info[] = {
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/* 8168E family. */
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{ 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
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{ 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
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{ 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
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{ 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
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@ -2664,7 +2703,7 @@ static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
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rtl_patchphy(tp, 0x0d, 1 << 5);
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}
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static void rtl8168e_hw_phy_config(struct rtl8169_private *tp)
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static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
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{
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static const struct phy_reg phy_reg_init[] = {
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/* Enable Delay cap */
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@ -2737,6 +2776,91 @@ static void rtl8168e_hw_phy_config(struct rtl8169_private *tp)
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rtl_writephy(tp, 0x0d, 0x0000);
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}
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static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
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{
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static const struct phy_reg phy_reg_init[] = {
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/* Enable Delay cap */
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{ 0x1f, 0x0004 },
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{ 0x1f, 0x0007 },
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{ 0x1e, 0x00ac },
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{ 0x18, 0x0006 },
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{ 0x1f, 0x0002 },
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{ 0x1f, 0x0000 },
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{ 0x1f, 0x0000 },
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/* Channel estimation fine tune */
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{ 0x1f, 0x0003 },
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{ 0x09, 0xa20f },
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{ 0x1f, 0x0000 },
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{ 0x1f, 0x0000 },
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/* Green Setting */
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{ 0x1f, 0x0005 },
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{ 0x05, 0x8b5b },
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{ 0x06, 0x9222 },
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{ 0x05, 0x8b6d },
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{ 0x06, 0x8000 },
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{ 0x05, 0x8b76 },
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{ 0x06, 0x8000 },
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{ 0x1f, 0x0000 }
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};
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rtl_apply_firmware(tp);
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rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
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/* For 4-corner performance improve */
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rtl_writephy(tp, 0x1f, 0x0005);
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rtl_writephy(tp, 0x05, 0x8b80);
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rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
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rtl_writephy(tp, 0x1f, 0x0000);
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/* PHY auto speed down */
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rtl_writephy(tp, 0x1f, 0x0004);
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rtl_writephy(tp, 0x1f, 0x0007);
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rtl_writephy(tp, 0x1e, 0x002d);
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rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
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rtl_writephy(tp, 0x1f, 0x0002);
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rtl_writephy(tp, 0x1f, 0x0000);
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rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
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/* improve 10M EEE waveform */
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rtl_writephy(tp, 0x1f, 0x0005);
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rtl_writephy(tp, 0x05, 0x8b86);
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rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
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rtl_writephy(tp, 0x1f, 0x0000);
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/* Improve 2-pair detection performance */
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rtl_writephy(tp, 0x1f, 0x0005);
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rtl_writephy(tp, 0x05, 0x8b85);
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rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
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rtl_writephy(tp, 0x1f, 0x0000);
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/* EEE setting */
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rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
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ERIAR_EXGMAC);
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rtl_writephy(tp, 0x1f, 0x0005);
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rtl_writephy(tp, 0x05, 0x8b85);
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rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
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rtl_writephy(tp, 0x1f, 0x0004);
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rtl_writephy(tp, 0x1f, 0x0007);
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rtl_writephy(tp, 0x1e, 0x0020);
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rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
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rtl_writephy(tp, 0x1f, 0x0002);
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rtl_writephy(tp, 0x1f, 0x0000);
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rtl_writephy(tp, 0x0d, 0x0007);
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rtl_writephy(tp, 0x0e, 0x003c);
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rtl_writephy(tp, 0x0d, 0x4007);
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rtl_writephy(tp, 0x0e, 0x0000);
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rtl_writephy(tp, 0x0d, 0x0000);
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/* Green feature */
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rtl_writephy(tp, 0x1f, 0x0003);
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rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
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rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
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rtl_writephy(tp, 0x1f, 0x0000);
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}
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static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
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{
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static const struct phy_reg phy_reg_init[] = {
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@ -2856,7 +2980,10 @@ static void rtl_hw_phy_config(struct net_device *dev)
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break;
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case RTL_GIGA_MAC_VER_32:
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case RTL_GIGA_MAC_VER_33:
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rtl8168e_hw_phy_config(tp);
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rtl8168e_1_hw_phy_config(tp);
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break;
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case RTL_GIGA_MAC_VER_34:
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rtl8168e_2_hw_phy_config(tp);
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break;
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default:
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@ -3362,6 +3489,7 @@ static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
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case RTL_GIGA_MAC_VER_31:
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case RTL_GIGA_MAC_VER_32:
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case RTL_GIGA_MAC_VER_33:
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case RTL_GIGA_MAC_VER_34:
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ops->down = r8168_pll_power_down;
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ops->up = r8168_pll_power_up;
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break;
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@ -3799,6 +3927,9 @@ static void rtl8169_hw_reset(struct rtl8169_private *tp)
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tp->mac_version == RTL_GIGA_MAC_VER_31) {
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while (RTL_R8(TxPoll) & NPQ)
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udelay(20);
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} else if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
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while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
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udelay(100);
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} else {
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RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
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udelay(100);
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@ -4210,9 +4341,9 @@ static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
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rtl_enable_clock_request(pdev);
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}
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static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev)
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static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
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{
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static const struct ephy_info e_info_8168e[] = {
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static const struct ephy_info e_info_8168e_1[] = {
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{ 0x00, 0x0200, 0x0100 },
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{ 0x00, 0x0000, 0x0004 },
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{ 0x06, 0x0002, 0x0001 },
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@ -4230,7 +4361,7 @@ static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev)
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rtl_csi_access_enable_2(ioaddr);
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rtl_ephy_init(ioaddr, e_info_8168e, ARRAY_SIZE(e_info_8168e));
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rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
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rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
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@ -4245,6 +4376,44 @@ static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev)
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RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
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}
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static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
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{
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static const struct ephy_info e_info_8168e_2[] = {
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{ 0x09, 0x0000, 0x0080 },
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{ 0x19, 0x0000, 0x0224 }
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};
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rtl_csi_access_enable_1(ioaddr);
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rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
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rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
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rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
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rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
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rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
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rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
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rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
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rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
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rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
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rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
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ERIAR_EXGMAC);
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RTL_W8(MaxTxPacketSize, 0x27);
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rtl_disable_clock_request(pdev);
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RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
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RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
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/* Adjust EEE LED frequency */
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RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
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RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
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RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
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RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
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}
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static void rtl_hw_start_8168(struct net_device *dev)
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{
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struct rtl8169_private *tp = netdev_priv(dev);
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@ -4333,7 +4502,10 @@ static void rtl_hw_start_8168(struct net_device *dev)
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case RTL_GIGA_MAC_VER_32:
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case RTL_GIGA_MAC_VER_33:
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rtl_hw_start_8168e(ioaddr, pdev);
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rtl_hw_start_8168e_1(ioaddr, pdev);
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break;
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case RTL_GIGA_MAC_VER_34:
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rtl_hw_start_8168e_2(ioaddr, pdev);
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break;
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default:
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