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powerpc: Add DIU platform code for MPC8610HPCD
Add platform code to support Freescale DIU. The platform code includes framebuffer memory allocation, pixel format, monitor port, etc. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Cc: Paul Mackerras <paulus@samba.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: "Antonino A. Daplas" <adaplas@pol.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
York Sun
Linus Torvalds
parent
9b53a9e28a
commit
6f90a8bdd1
@ -3,11 +3,12 @@
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*
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* Initial author: Xianghua Xiao <x.xiao@freescale.com>
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* Recode: Jason Jin <jason.jin@freescale.com>
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* York Sun <yorksun@freescale.com>
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*
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* Rewrite the interrupt routing. remove the 8259PIC support,
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* All the integrated device in ULI use sideband interrupt.
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*
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* Copyright 2007 Freescale Semiconductor Inc.
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* Copyright 2008 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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@ -38,6 +39,8 @@
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#include <sysdev/fsl_pci.h>
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#include <sysdev/fsl_soc.h>
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static unsigned char *pixis_bdcfg0, *pixis_arch;
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static struct of_device_id __initdata mpc8610_ids[] = {
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{ .compatible = "fsl,mpc8610-immr", },
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{}
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@ -52,8 +55,7 @@ static int __init mpc8610_declare_of_platform_devices(void)
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}
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machine_device_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices);
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static void __init
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mpc86xx_hpcd_init_irq(void)
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static void __init mpc86xx_hpcd_init_irq(void)
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{
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struct mpic *mpic1;
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struct device_node *np;
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@ -161,12 +163,159 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5288, final_uli5288);
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#endif /* CONFIG_PCI */
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static void __init
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mpc86xx_hpcd_setup_arch(void)
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#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
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static u32 get_busfreq(void)
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{
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#ifdef CONFIG_PCI
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struct device_node *np;
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struct device_node *node;
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u32 fs_busfreq = 0;
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node = of_find_node_by_type(NULL, "cpu");
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if (node) {
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unsigned int size;
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const unsigned int *prop =
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of_get_property(node, "bus-frequency", &size);
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if (prop)
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fs_busfreq = *prop;
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of_node_put(node);
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};
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return fs_busfreq;
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}
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unsigned int mpc8610hpcd_get_pixel_format(unsigned int bits_per_pixel,
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int monitor_port)
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{
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static const unsigned long pixelformat[][3] = {
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{0x88882317, 0x88083218, 0x65052119},
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{0x88883316, 0x88082219, 0x65053118},
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};
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unsigned int pix_fmt, arch_monitor;
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arch_monitor = ((*pixis_arch == 0x01) && (monitor_port == 0))? 0 : 1;
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/* DVI port for board version 0x01 */
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if (bits_per_pixel == 32)
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pix_fmt = pixelformat[arch_monitor][0];
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else if (bits_per_pixel == 24)
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pix_fmt = pixelformat[arch_monitor][1];
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else if (bits_per_pixel == 16)
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pix_fmt = pixelformat[arch_monitor][2];
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else
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pix_fmt = pixelformat[1][0];
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return pix_fmt;
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}
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void mpc8610hpcd_set_gamma_table(int monitor_port, char *gamma_table_base)
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{
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int i;
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if (monitor_port == 2) { /* dual link LVDS */
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for (i = 0; i < 256*3; i++)
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gamma_table_base[i] = (gamma_table_base[i] << 2) |
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((gamma_table_base[i] >> 6) & 0x03);
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}
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}
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void mpc8610hpcd_set_monitor_port(int monitor_port)
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{
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static const u8 bdcfg[] = {0xBD, 0xB5, 0xA5};
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if (monitor_port < 3)
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*pixis_bdcfg0 = bdcfg[monitor_port];
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}
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void mpc8610hpcd_set_pixel_clock(unsigned int pixclock)
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{
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u32 __iomem *clkdvdr;
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u32 temp;
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/* variables for pixel clock calcs */
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ulong bestval, bestfreq, speed_ccb, minpixclock, maxpixclock;
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ulong pixval;
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long err;
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int i;
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clkdvdr = ioremap(get_immrbase() + 0xe0800, sizeof(u32));
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if (!clkdvdr) {
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printk(KERN_ERR "Err: can't map clock divider register!\n");
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return;
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}
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/* Pixel Clock configuration */
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pr_debug("DIU: Bus Frequency = %d\n", get_busfreq());
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speed_ccb = get_busfreq();
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/* Calculate the pixel clock with the smallest error */
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/* calculate the following in steps to avoid overflow */
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pr_debug("DIU pixclock in ps - %d\n", pixclock);
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temp = 1000000000/pixclock;
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temp *= 1000;
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pixclock = temp;
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pr_debug("DIU pixclock freq - %u\n", pixclock);
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temp = pixclock * 5 / 100;
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pr_debug("deviation = %d\n", temp);
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minpixclock = pixclock - temp;
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maxpixclock = pixclock + temp;
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pr_debug("DIU minpixclock - %lu\n", minpixclock);
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pr_debug("DIU maxpixclock - %lu\n", maxpixclock);
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pixval = speed_ccb/pixclock;
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pr_debug("DIU pixval = %lu\n", pixval);
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err = 100000000;
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bestval = pixval;
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pr_debug("DIU bestval = %lu\n", bestval);
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bestfreq = 0;
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for (i = -1; i <= 1; i++) {
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temp = speed_ccb / ((pixval+i) + 1);
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pr_debug("DIU test pixval i= %d, pixval=%lu, temp freq. = %u\n",
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i, pixval, temp);
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if ((temp < minpixclock) || (temp > maxpixclock))
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pr_debug("DIU exceeds monitor range (%lu to %lu)\n",
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minpixclock, maxpixclock);
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else if (abs(temp - pixclock) < err) {
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pr_debug("Entered the else if block %d\n", i);
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err = abs(temp - pixclock);
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bestval = pixval+i;
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bestfreq = temp;
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}
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}
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pr_debug("DIU chose = %lx\n", bestval);
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pr_debug("DIU error = %ld\n NomPixClk ", err);
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pr_debug("DIU: Best Freq = %lx\n", bestfreq);
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/* Modify PXCLK in GUTS CLKDVDR */
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pr_debug("DIU: Current value of CLKDVDR = 0x%08x\n", (*clkdvdr));
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temp = (*clkdvdr) & 0x2000FFFF;
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*clkdvdr = temp; /* turn off clock */
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*clkdvdr = temp | 0x80000000 | (((bestval) & 0x1F) << 16);
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pr_debug("DIU: Modified value of CLKDVDR = 0x%08x\n", (*clkdvdr));
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iounmap(clkdvdr);
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}
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ssize_t mpc8610hpcd_show_monitor_port(int monitor_port, char *buf)
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{
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return snprintf(buf, PAGE_SIZE,
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"%c0 - DVI\n"
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"%c1 - Single link LVDS\n"
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"%c2 - Dual link LVDS\n",
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monitor_port == 0 ? '*' : ' ',
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monitor_port == 1 ? '*' : ' ',
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monitor_port == 2 ? '*' : ' ');
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}
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int mpc8610hpcd_set_sysfs_monitor_port(int val)
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{
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return val < 3 ? val : 0;
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}
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#endif
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static void __init mpc86xx_hpcd_setup_arch(void)
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{
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struct resource r;
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struct device_node *np;
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unsigned char *pixis;
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if (ppc_md.progress)
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ppc_md.progress("mpc86xx_hpcd_setup_arch()", 0);
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@ -183,6 +332,30 @@ mpc86xx_hpcd_setup_arch(void)
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}
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}
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#endif
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#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
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preallocate_diu_videomemory();
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diu_ops.get_pixel_format = mpc8610hpcd_get_pixel_format;
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diu_ops.set_gamma_table = mpc8610hpcd_set_gamma_table;
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diu_ops.set_monitor_port = mpc8610hpcd_set_monitor_port;
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diu_ops.set_pixel_clock = mpc8610hpcd_set_pixel_clock;
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diu_ops.show_monitor_port = mpc8610hpcd_show_monitor_port;
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diu_ops.set_sysfs_monitor_port = mpc8610hpcd_set_sysfs_monitor_port;
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#endif
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np = of_find_compatible_node(NULL, NULL, "fsl,fpga-pixis");
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if (np) {
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of_address_to_resource(np, 0, &r);
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of_node_put(np);
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pixis = ioremap(r.start, 32);
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if (!pixis) {
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printk(KERN_ERR "Err: can't map FPGA cfg register!\n");
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return;
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}
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pixis_bdcfg0 = pixis + 8;
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pixis_arch = pixis + 1;
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} else
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printk(KERN_ERR "Err: "
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"can't find device node 'fsl,fpga-pixis'\n");
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printk("MPC86xx HPCD board from Freescale Semiconductor\n");
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}
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@ -200,8 +373,7 @@ static int __init mpc86xx_hpcd_probe(void)
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return 0;
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}
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static long __init
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mpc86xx_time_init(void)
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static long __init mpc86xx_time_init(void)
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{
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unsigned int temp;
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@ -892,3 +892,44 @@ void fsl_rstcr_restart(char *cmd)
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while (1) ;
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}
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#endif
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#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
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struct platform_diu_data_ops diu_ops = {
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.diu_size = 1280 * 1024 * 4, /* default one 1280x1024 buffer */
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};
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EXPORT_SYMBOL(diu_ops);
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int __init preallocate_diu_videomemory(void)
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{
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pr_debug("diu_size=%lu\n", diu_ops.diu_size);
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diu_ops.diu_mem = __alloc_bootmem(diu_ops.diu_size, 8, 0);
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if (!diu_ops.diu_mem) {
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printk(KERN_ERR "fsl-diu: cannot allocate %lu bytes\n",
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diu_ops.diu_size);
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return -ENOMEM;
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}
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pr_debug("diu_mem=%p\n", diu_ops.diu_mem);
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rh_init(&diu_ops.diu_rh_info, 4096, ARRAY_SIZE(diu_ops.diu_rh_block),
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diu_ops.diu_rh_block);
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return rh_attach_region(&diu_ops.diu_rh_info,
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(unsigned long) diu_ops.diu_mem,
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diu_ops.diu_size);
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}
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static int __init early_parse_diufb(char *p)
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{
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if (!p)
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return 1;
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diu_ops.diu_size = _ALIGN_UP(memparse(p, &p), 8);
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pr_debug("diu_size=%lu\n", diu_ops.diu_size);
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return 0;
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}
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early_param("diufb", early_parse_diufb);
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#endif
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@ -17,5 +17,28 @@ extern int fsl_spi_init(struct spi_board_info *board_infos,
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void (*deactivate_cs)(u8 cs, u8 polarity));
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extern void fsl_rstcr_restart(char *cmd);
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#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
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#include <linux/bootmem.h>
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#include <asm/rheap.h>
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struct platform_diu_data_ops {
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rh_block_t diu_rh_block[16];
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rh_info_t diu_rh_info;
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unsigned long diu_size;
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void *diu_mem;
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unsigned int (*get_pixel_format) (unsigned int bits_per_pixel,
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int monitor_port);
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void (*set_gamma_table) (int monitor_port, char *gamma_table_base);
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void (*set_monitor_port) (int monitor_port);
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void (*set_pixel_clock) (unsigned int pixclock);
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ssize_t (*show_monitor_port) (int monitor_port, char *buf);
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int (*set_sysfs_monitor_port) (int val);
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};
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extern struct platform_diu_data_ops diu_ops;
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int __init preallocate_diu_videomemory(void);
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#endif
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#endif
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#endif
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