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i2c: at91: fix write transfers by clearing pending interrupt first
In some cases a NACK interrupt may be pending in the Status Register (SR)
as a result of a previous transfer. However at91_do_twi_transfer() did not
read the SR to clear pending interruptions before starting a new transfer.
Hence a NACK interrupt rose as soon as it was enabled again at the I2C
controller level, resulting in a wrong sequence of operations and strange
patterns of behaviour on the I2C bus, such as a clock stretch followed by
a restart of the transfer.
This first issue occurred with both DMA and PIO write transfers.
Also when a NACK error was detected during a PIO write transfer, the
interrupt handler used to wrongly start a new transfer by writing into the
Transmit Holding Register (THR). Then the I2C slave was likely to reply
with a second NACK.
This second issue is fixed in atmel_twi_interrupt() by handling the TXRDY
status bit only if both the TXCOMP and NACK status bits are cleared.
Tested with a at24 eeprom on sama5d36ek board running a linux-4.1-at91
kernel image. Adapted to linux-next.
Reported-by: Peter Rosin <peda@lysator.liu.se>
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Tested-by: Peter Rosin <peda@lysator.liu.se>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Fixes: 93563a6a71
("i2c: at91: fix a race condition when using the DMA controller")
Cc: stable@vger.kernel.org #4.1
This commit is contained in:
parent
319d7f05df
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@ -465,19 +465,57 @@ static irqreturn_t atmel_twi_interrupt(int irq, void *dev_id)
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if (!irqstatus)
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return IRQ_NONE;
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else if (irqstatus & AT91_TWI_RXRDY)
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at91_twi_read_next_byte(dev);
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else if (irqstatus & AT91_TWI_TXRDY)
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at91_twi_write_next_byte(dev);
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/* catch error flags */
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dev->transfer_status |= status;
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/*
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* When a NACK condition is detected, the I2C controller sets the NACK,
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* TXCOMP and TXRDY bits all together in the Status Register (SR).
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*
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* 1 - Handling NACK errors with CPU write transfer.
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*
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* In such case, we should not write the next byte into the Transmit
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* Holding Register (THR) otherwise the I2C controller would start a new
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* transfer and the I2C slave is likely to reply by another NACK.
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*
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* 2 - Handling NACK errors with DMA write transfer.
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*
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* By setting the TXRDY bit in the SR, the I2C controller also triggers
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* the DMA controller to write the next data into the THR. Then the
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* result depends on the hardware version of the I2C controller.
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*
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* 2a - Without support of the Alternative Command mode.
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*
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* This is the worst case: the DMA controller is triggered to write the
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* next data into the THR, hence starting a new transfer: the I2C slave
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* is likely to reply by another NACK.
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* Concurrently, this interrupt handler is likely to be called to manage
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* the first NACK before the I2C controller detects the second NACK and
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* sets once again the NACK bit into the SR.
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* When handling the first NACK, this interrupt handler disables the I2C
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* controller interruptions, especially the NACK interrupt.
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* Hence, the NACK bit is pending into the SR. This is why we should
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* read the SR to clear all pending interrupts at the beginning of
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* at91_do_twi_transfer() before actually starting a new transfer.
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*
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* 2b - With support of the Alternative Command mode.
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*
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* When a NACK condition is detected, the I2C controller also locks the
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* THR (and sets the LOCK bit in the SR): even though the DMA controller
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* is triggered by the TXRDY bit to write the next data into the THR,
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* this data actually won't go on the I2C bus hence a second NACK is not
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* generated.
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*/
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if (irqstatus & (AT91_TWI_TXCOMP | AT91_TWI_NACK)) {
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at91_disable_twi_interrupts(dev);
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complete(&dev->cmd_complete);
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} else if (irqstatus & AT91_TWI_RXRDY) {
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at91_twi_read_next_byte(dev);
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} else if (irqstatus & AT91_TWI_TXRDY) {
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at91_twi_write_next_byte(dev);
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}
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/* catch error flags */
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dev->transfer_status |= status;
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return IRQ_HANDLED;
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}
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@ -487,6 +525,7 @@ static int at91_do_twi_transfer(struct at91_twi_dev *dev)
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unsigned long time_left;
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bool has_unre_flag = dev->pdata->has_unre_flag;
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bool has_alt_cmd = dev->pdata->has_alt_cmd;
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unsigned sr;
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/*
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* WARNING: the TXCOMP bit in the Status Register is NOT a clear on
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@ -537,6 +576,9 @@ static int at91_do_twi_transfer(struct at91_twi_dev *dev)
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reinit_completion(&dev->cmd_complete);
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dev->transfer_status = 0;
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/* Clear pending interrupts, such as NACK. */
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sr = at91_twi_read(dev, AT91_TWI_SR);
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if (dev->fifo_size) {
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unsigned fifo_mr = at91_twi_read(dev, AT91_TWI_FMR);
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@ -558,7 +600,7 @@ static int at91_do_twi_transfer(struct at91_twi_dev *dev)
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} else if (dev->msg->flags & I2C_M_RD) {
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unsigned start_flags = AT91_TWI_START;
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if (at91_twi_read(dev, AT91_TWI_SR) & AT91_TWI_RXRDY) {
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if (sr & AT91_TWI_RXRDY) {
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dev_err(dev->dev, "RXRDY still set!");
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at91_twi_read(dev, AT91_TWI_RHR);
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}
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