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KVM: PPC: Book3S PR: Add guest MSR parameter for kvmppc_save_tm()/kvmppc_restore_tm()
HV KVM and PR KVM need different MSR source to indicate whether
treclaim. or trecheckpoint. is necessary.
This patch add new parameter (guest MSR) for these kvmppc_save_tm/
kvmppc_restore_tm() APIs:
- For HV KVM, it is VCPU_MSR
- For PR KVM, it is current host MSR or VCPU_SHADOW_SRR1
This enhancement enables these 2 APIs to be reused by PR KVM later.
And the patch keeps HV KVM logic unchanged.
This patch also reworks kvmppc_save_tm()/kvmppc_restore_tm() to
have a clean ABI: r3 for vcpu and r4 for guest_msr.
During kvmppc_save_tm/kvmppc_restore_tm(), the R1 need to be saved
or restored. Currently the R1 is saved into HSTATE_HOST_R1. In PR
KVM, we are going to add a C function wrapper for
kvmppc_save_tm/kvmppc_restore_tm() where the R1 will be incremented
with added stackframe and save into HSTATE_HOST_R1. There are several
places in HV KVM to load HSTATE_HOST_R1 as R1, and we don't want to
bring risk or confusion by TM code.
This patch will use HSTATE_SCRATCH2 to save/restore R1 in
kvmppc_save_tm/kvmppc_restore_tm() to avoid future confusion, since
the r1 is actually a temporary/scratch value to be saved/stored.
[paulus@ozlabs.org - rebased on top of 7b0e827c69 ("KVM: PPC: Book3S HV:
Factor fake-suspend handling out of kvmppc_save/restore_tm", 2018-05-30)]
Signed-off-by: Simon Guo <wei.guo.simon@gmail.com>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This commit is contained in:
Simon Guo
Paul Mackerras
parent
009c872a8b
commit
6f597c6b63
@ -793,7 +793,10 @@ END_FTR_SECTION(CPU_FTR_TM | CPU_FTR_P9_TM_HV_ASSIST, 0)
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/*
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* NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS INCLUDING CR
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*/
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mr r3, r4
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ld r4, VCPU_MSR(r3)
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bl kvmppc_restore_tm_hv
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ld r4, HSTATE_KVM_VCPU(r13)
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91:
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#endif
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@ -1777,7 +1780,10 @@ END_FTR_SECTION(CPU_FTR_TM | CPU_FTR_P9_TM_HV_ASSIST, 0)
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/*
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* NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS INCLUDING CR
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*/
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mr r3, r9
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ld r4, VCPU_MSR(r3)
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bl kvmppc_save_tm_hv
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ld r9, HSTATE_KVM_VCPU(r13)
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91:
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#endif
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@ -2680,7 +2686,8 @@ END_FTR_SECTION(CPU_FTR_TM | CPU_FTR_P9_TM_HV_ASSIST, 0)
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/*
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* NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS INCLUDING CR
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*/
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ld r9, HSTATE_KVM_VCPU(r13)
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ld r3, HSTATE_KVM_VCPU(r13)
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ld r4, VCPU_MSR(r3)
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bl kvmppc_save_tm_hv
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91:
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#endif
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@ -2799,7 +2806,10 @@ END_FTR_SECTION(CPU_FTR_TM | CPU_FTR_P9_TM_HV_ASSIST, 0)
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/*
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* NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS INCLUDING CR
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*/
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mr r3, r4
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ld r4, VCPU_MSR(r3)
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bl kvmppc_restore_tm_hv
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ld r4, HSTATE_KVM_VCPU(r13)
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91:
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#endif
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@ -3120,9 +3130,10 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
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#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
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/*
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* Save transactional state and TM-related registers.
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* Called with r9 pointing to the vcpu struct.
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* Called with r3 pointing to the vcpu struct and r4 containing
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* the guest MSR value.
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* This can modify all checkpointed registers, but
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* restores r1, r2 and r9 (vcpu pointer) before exit.
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* restores r1 and r2 before exit.
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*/
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kvmppc_save_tm_hv:
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/* See if we need to handle fake suspend mode */
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@ -3205,9 +3216,10 @@ END_FTR_SECTION_NESTED(CPU_FTR_P9_TM_XER_SO_BUG, CPU_FTR_P9_TM_XER_SO_BUG, 96)
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/*
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* Restore transactional state and TM-related registers.
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* Called with r4 pointing to the vcpu struct.
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* Called with r3 pointing to the vcpu struct
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* and r4 containing the guest MSR value.
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* This potentially modifies all checkpointed registers.
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* It restores r1, r2, r4 from the PACA.
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* It restores r1 and r2 from the PACA.
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*/
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kvmppc_restore_tm_hv:
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/*
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@ -3234,15 +3246,14 @@ END_FTR_SECTION_IFCLR(CPU_FTR_P9_TM_HV_ASSIST)
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* The user may change these outside of a transaction, so they must
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* always be context switched.
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*/
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ld r5, VCPU_TFHAR(r4)
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ld r6, VCPU_TFIAR(r4)
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ld r7, VCPU_TEXASR(r4)
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ld r5, VCPU_TFHAR(r3)
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ld r6, VCPU_TFIAR(r3)
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ld r7, VCPU_TEXASR(r3)
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mtspr SPRN_TFHAR, r5
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mtspr SPRN_TFIAR, r6
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mtspr SPRN_TEXASR, r7
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ld r5, VCPU_MSR(r4)
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rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
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rldicl. r5, r4, 64 - MSR_TS_S_LG, 62
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beqlr /* TM not active in guest */
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/* Make sure the failure summary is set */
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@ -3255,10 +3266,8 @@ END_FTR_SECTION_IFCLR(CPU_FTR_P9_TM_HV_ASSIST)
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b 9f /* and return */
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10: stdu r1, -PPC_MIN_STKFRM(r1)
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/* guest is in transactional state, so simulate rollback */
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mr r3, r4
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bl kvmhv_emulate_tm_rollback
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nop
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ld r4, HSTATE_KVM_VCPU(r13) /* our vcpu pointer has been trashed */
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addi r1, r1, PPC_MIN_STKFRM
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9: ld r0, PPC_LR_STKOFF(r1)
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mtlr r0
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@ -26,9 +26,12 @@
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/*
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* Save transactional state and TM-related registers.
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* Called with r9 pointing to the vcpu struct.
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* Called with:
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* - r3 pointing to the vcpu struct
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* - r4 points to the MSR with current TS bits:
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* (For HV KVM, it is VCPU_MSR ; For PR KVM, it is host MSR).
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* This can modify all checkpointed registers, but
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* restores r1, r2 and r9 (vcpu pointer) before exit.
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* restores r1, r2 before exit.
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*/
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_GLOBAL(kvmppc_save_tm)
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mflr r0
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@ -40,20 +43,17 @@ _GLOBAL(kvmppc_save_tm)
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rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
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mtmsrd r8
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#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
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ld r5, VCPU_MSR(r9)
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rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
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rldicl. r4, r4, 64 - MSR_TS_S_LG, 62
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beq 1f /* TM not active in guest. */
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#endif
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std r1, HSTATE_HOST_R1(r13)
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li r3, TM_CAUSE_KVM_RESCHED
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std r1, HSTATE_SCRATCH2(r13)
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std r3, HSTATE_SCRATCH1(r13)
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#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
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BEGIN_FTR_SECTION
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/* Emulation of the treclaim instruction needs TEXASR before treclaim */
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mfspr r6, SPRN_TEXASR
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std r6, VCPU_ORIG_TEXASR(r9)
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std r6, VCPU_ORIG_TEXASR(r3)
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END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_HV_ASSIST)
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#endif
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@ -61,6 +61,8 @@ END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_HV_ASSIST)
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li r5, 0
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mtmsrd r5, 1
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li r3, TM_CAUSE_KVM_RESCHED
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/* All GPRs are volatile at this point. */
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TRECLAIM(R3)
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@ -68,9 +70,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_HV_ASSIST)
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SET_SCRATCH0(r13)
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GET_PACA(r13)
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std r9, PACATMSCRATCH(r13)
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#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
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ld r9, HSTATE_KVM_VCPU(r13)
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#endif
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ld r9, HSTATE_SCRATCH1(r13)
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/* Get a few more GPRs free. */
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std r29, VCPU_GPRS_TM(29)(r9)
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@ -102,7 +102,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_HV_ASSIST)
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std r4, VCPU_GPRS_TM(9)(r9)
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/* Reload stack pointer and TOC. */
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ld r1, HSTATE_HOST_R1(r13)
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ld r1, HSTATE_SCRATCH2(r13)
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ld r2, PACATOC(r13)
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/* Set MSR RI now we have r1 and r13 back. */
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@ -156,9 +156,13 @@ END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_HV_ASSIST)
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/*
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* Restore transactional state and TM-related registers.
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* Called with r4 pointing to the vcpu struct.
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* Called with:
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* - r3 pointing to the vcpu struct.
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* - r4 is the guest MSR with desired TS bits:
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* For HV KVM, it is VCPU_MSR
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* For PR KVM, it is provided by caller
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* This potentially modifies all checkpointed registers.
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* It restores r1, r2, r4 from the PACA.
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* It restores r1, r2 from the PACA.
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*/
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_GLOBAL(kvmppc_restore_tm)
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mflr r0
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@ -177,19 +181,17 @@ _GLOBAL(kvmppc_restore_tm)
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* The user may change these outside of a transaction, so they must
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* always be context switched.
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*/
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ld r5, VCPU_TFHAR(r4)
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ld r6, VCPU_TFIAR(r4)
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ld r7, VCPU_TEXASR(r4)
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ld r5, VCPU_TFHAR(r3)
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ld r6, VCPU_TFIAR(r3)
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ld r7, VCPU_TEXASR(r3)
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mtspr SPRN_TFHAR, r5
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mtspr SPRN_TFIAR, r6
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mtspr SPRN_TEXASR, r7
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#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
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ld r5, VCPU_MSR(r4)
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mr r5, r4
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rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
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beqlr /* TM not active in guest */
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#endif
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std r1, HSTATE_HOST_R1(r13)
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std r1, HSTATE_SCRATCH2(r13)
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/* Make sure the failure summary is set, otherwise we'll program check
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* when we trechkpt. It's possible that this might have been not set
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@ -205,21 +207,21 @@ _GLOBAL(kvmppc_restore_tm)
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* some SPRs.
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*/
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mr r31, r4
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mr r31, r3
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addi r3, r31, VCPU_FPRS_TM
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bl load_fp_state
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addi r3, r31, VCPU_VRS_TM
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bl load_vr_state
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mr r4, r31
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lwz r7, VCPU_VRSAVE_TM(r4)
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mr r3, r31
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lwz r7, VCPU_VRSAVE_TM(r3)
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mtspr SPRN_VRSAVE, r7
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ld r5, VCPU_LR_TM(r4)
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lwz r6, VCPU_CR_TM(r4)
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ld r7, VCPU_CTR_TM(r4)
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ld r8, VCPU_AMR_TM(r4)
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ld r9, VCPU_TAR_TM(r4)
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ld r10, VCPU_XER_TM(r4)
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ld r5, VCPU_LR_TM(r3)
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lwz r6, VCPU_CR_TM(r3)
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ld r7, VCPU_CTR_TM(r3)
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ld r8, VCPU_AMR_TM(r3)
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ld r9, VCPU_TAR_TM(r3)
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ld r10, VCPU_XER_TM(r3)
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mtlr r5
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mtcr r6
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mtctr r7
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@ -232,8 +234,8 @@ _GLOBAL(kvmppc_restore_tm)
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* till the last moment to avoid running with userspace PPR and DSCR for
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* too long.
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*/
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ld r29, VCPU_DSCR_TM(r4)
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ld r30, VCPU_PPR_TM(r4)
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ld r29, VCPU_DSCR_TM(r3)
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ld r30, VCPU_PPR_TM(r3)
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std r2, PACATMSCRATCH(r13) /* Save TOC */
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@ -265,9 +267,8 @@ _GLOBAL(kvmppc_restore_tm)
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#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
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ld r29, HSTATE_DSCR(r13)
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mtspr SPRN_DSCR, r29
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ld r4, HSTATE_KVM_VCPU(r13)
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#endif
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ld r1, HSTATE_HOST_R1(r13)
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ld r1, HSTATE_SCRATCH2(r13)
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ld r2, PACATMSCRATCH(r13)
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/* Set the MSR RI since we have our registers back. */
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