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ASoC: Intel: Add Baytrail SST ID and Baytrail specific register bits
While the SHIM register addresses in Baytrail are the same than Haswell and Broadwell their register size is 64-bit and some bits are different. This patch adds the SST device ID for Baytrail and Baytrail specific SHIM bit definitions. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Acked-by: Liam Girdwood <liam.r.girdwood@intel.com> Signed-off-by: Mark Brown <broonie@linaro.org>
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@ -24,6 +24,7 @@
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/* SST Device IDs */
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#define SST_DEV_ID_LYNX_POINT 0x33C8
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#define SST_DEV_ID_WILDCAT_POINT 0x3438
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#define SST_DEV_ID_BYT 0x0F28
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/* Supported SST DMA Devices */
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#define SST_DMA_TYPE_DW 1
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@ -72,10 +73,15 @@
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#define SST_CSR_S0IOCS (0x1 << 21)
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#define SST_CSR_S1IOCS (0x1 << 23)
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#define SST_CSR_LPCS (0x1 << 31)
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#define SST_BYT_CSR_RST (0x1 << 0)
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#define SST_BYT_CSR_VECTOR_SEL (0x1 << 1)
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#define SST_BYT_CSR_STALL (0x1 << 2)
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#define SST_BYT_CSR_PWAITMODE (0x1 << 3)
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/* ISRX / ISC */
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#define SST_ISRX_BUSY (0x1 << 1)
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#define SST_ISRX_DONE (0x1 << 0)
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#define SST_BYT_ISRX_REQUEST (0x1 << 1)
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/* ISRD / ISD */
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#define SST_ISRD_BUSY (0x1 << 1)
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@ -84,14 +90,19 @@
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/* IMRX / IMC */
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#define SST_IMRX_BUSY (0x1 << 1)
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#define SST_IMRX_DONE (0x1 << 0)
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#define SST_BYT_IMRX_REQUEST (0x1 << 1)
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/* IPCX / IPCC */
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#define SST_IPCX_DONE (0x1 << 30)
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#define SST_IPCX_BUSY (0x1 << 31)
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#define SST_BYT_IPCX_DONE ((u64)0x1 << 62)
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#define SST_BYT_IPCX_BUSY ((u64)0x1 << 63)
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/* IPCD */
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#define SST_IPCD_DONE (0x1 << 30)
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#define SST_IPCD_BUSY (0x1 << 31)
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#define SST_BYT_IPCD_DONE ((u64)0x1 << 62)
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#define SST_BYT_IPCD_BUSY ((u64)0x1 << 63)
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/* CLKCTL */
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#define SST_CLKCTL_SMOS(x) (x << 24)
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