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clk: ingenic: jz4770: Add 150us delay after enabling VPU clock

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This is required, as we must not use the AHB1 bus before it is stable.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Paul Cercueil 2018-05-20 16:31:17 +00:00 committed by Stephen Boyd
parent a6523b6fb8
commit 6ee3d385c2
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/ingenic/jz4770-cgu.c
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@ -362,7 +362,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
[JZ4770_CLK_VPU] = {
"vpu", CGU_CLK_GATE,
.parents = { JZ4770_CLK_H1CLK, },
.gate = { CGU_REG_LCR, 30 },
.gate = { CGU_REG_LCR, 30, false, 150 },
},
[JZ4770_CLK_MMC0] = {
"mmc0", CGU_CLK_GATE,