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Add PDM/DSD/dataline configuration support
Merge series from Shengjiu Wang <shengjiu.wang@nxp.com>: Support PDM format and DSD format. Add new dts property to configure dataline. The SAI has multiple successive FIFO registers, but in some use case the required dataline/FIFOs are not successive.
This commit is contained in:
Mark Brown
commit
6ed91f5b10
@ -49,6 +49,14 @@ Required properties:
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receive data by following their own bit clocks and
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frame sync clocks separately.
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- fsl,dataline : configure the dataline. it has 3 value for each configuration
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first one means the type: I2S(1) or PDM(2)
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second one is dataline mask for 'rx'
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third one is dataline mask for 'tx'.
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for example: fsl,dataline = <1 0xff 0xff 2 0xff 0x11>;
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it means I2S type rx mask is 0xff, tx mask is 0xff, PDM type
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rx mask is 0xff, tx mask is 0x11 (dataline 1 and 4 enabled).
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Optional properties:
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- big-endian : Boolean property, required if all the SAI
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@ -10,6 +10,7 @@
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/pm_qos.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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@ -30,7 +31,8 @@
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static const unsigned int fsl_sai_rates[] = {
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8000, 11025, 12000, 16000, 22050,
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24000, 32000, 44100, 48000, 64000,
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88200, 96000, 176400, 192000
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88200, 96000, 176400, 192000, 352800,
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384000, 705600, 768000, 1411200, 2822400,
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};
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static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = {
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@ -56,6 +58,31 @@ static inline bool fsl_sai_dir_is_synced(struct fsl_sai *sai, int dir)
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return !sai->synchronous[dir] && sai->synchronous[adir];
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}
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static struct pinctrl_state *fsl_sai_get_pins_state(struct fsl_sai *sai, u32 bclk)
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{
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struct pinctrl_state *state = 0;
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if (sai->is_pdm_mode) {
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/* DSD512@44.1kHz, DSD512@48kHz */
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if (bclk >= 22579200)
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state = pinctrl_lookup_state(sai->pinctrl, "dsd512");
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/* Get default DSD state */
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if (IS_ERR_OR_NULL(state))
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state = pinctrl_lookup_state(sai->pinctrl, "dsd");
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} else {
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/* 706k32b2c, 768k32b2c, etc */
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if (bclk >= 45158400)
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state = pinctrl_lookup_state(sai->pinctrl, "pcm_b2m");
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}
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/* Get default state */
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if (IS_ERR_OR_NULL(state))
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state = pinctrl_lookup_state(sai->pinctrl, "default");
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return state;
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}
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static irqreturn_t fsl_sai_isr(int irq, void *devid)
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{
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struct fsl_sai *sai = (struct fsl_sai *)devid;
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@ -224,6 +251,7 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
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if (!sai->is_lsb_first)
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val_cr4 |= FSL_SAI_CR4_MF;
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sai->is_pdm_mode = false;
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/* DAI mode */
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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@ -262,6 +290,11 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
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val_cr2 |= FSL_SAI_CR2_BCP;
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sai->is_dsp_mode = true;
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break;
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case SND_SOC_DAIFMT_PDM:
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val_cr2 |= FSL_SAI_CR2_BCP;
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val_cr4 &= ~FSL_SAI_CR4_MF;
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sai->is_pdm_mode = true;
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break;
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case SND_SOC_DAIFMT_RIGHT_J:
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/* To be done */
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default:
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@ -454,13 +487,18 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
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unsigned int ofs = sai->soc_data->reg_offset;
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bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
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unsigned int channels = params_channels(params);
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struct snd_dmaengine_dai_dma_data *dma_params;
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struct fsl_sai_dl_cfg *dl_cfg = sai->dl_cfg;
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u32 word_width = params_width(params);
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int trce_mask = 0, dl_cfg_idx = 0;
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int dl_cfg_cnt = sai->dl_cfg_cnt;
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u32 dl_type = FSL_SAI_DL_I2S;
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u32 val_cr4 = 0, val_cr5 = 0;
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u32 slots = (channels == 1) ? 2 : channels;
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u32 slot_width = word_width;
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int adir = tx ? RX : TX;
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u32 pins;
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int ret;
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u32 pins, bclk;
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int ret, i;
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if (sai->slots)
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slots = sai->slots;
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@ -470,15 +508,42 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
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pins = DIV_ROUND_UP(channels, slots);
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/*
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* PDM mode, channels are independent
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* each channels are on one dataline/FIFO.
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*/
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if (sai->is_pdm_mode) {
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pins = channels;
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dl_type = FSL_SAI_DL_PDM;
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}
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for (i = 0; i < dl_cfg_cnt; i++) {
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if (dl_cfg[i].type == dl_type && dl_cfg[i].pins[tx] == pins) {
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dl_cfg_idx = i;
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break;
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}
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}
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if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) < pins) {
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dev_err(cpu_dai->dev, "channel not supported\n");
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return -EINVAL;
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}
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bclk = params_rate(params) * (sai->bclk_ratio ? sai->bclk_ratio : slots * slot_width);
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if (!IS_ERR_OR_NULL(sai->pinctrl)) {
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sai->pins_state = fsl_sai_get_pins_state(sai, bclk);
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if (!IS_ERR_OR_NULL(sai->pins_state)) {
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ret = pinctrl_select_state(sai->pinctrl, sai->pins_state);
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if (ret) {
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dev_err(cpu_dai->dev, "failed to set proper pins state: %d\n", ret);
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return ret;
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}
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}
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}
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if (!sai->is_consumer_mode) {
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if (sai->bclk_ratio)
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ret = fsl_sai_set_bclk(cpu_dai, tx,
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sai->bclk_ratio *
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params_rate(params));
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else
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ret = fsl_sai_set_bclk(cpu_dai, tx,
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slots * slot_width *
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params_rate(params));
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ret = fsl_sai_set_bclk(cpu_dai, tx, bclk);
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if (ret)
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return ret;
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@ -492,13 +557,13 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
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}
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}
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if (!sai->is_dsp_mode)
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if (!sai->is_dsp_mode && !sai->is_pdm_mode)
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val_cr4 |= FSL_SAI_CR4_SYWD(slot_width);
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val_cr5 |= FSL_SAI_CR5_WNW(slot_width);
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val_cr5 |= FSL_SAI_CR5_W0W(slot_width);
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if (sai->is_lsb_first)
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if (sai->is_lsb_first || sai->is_pdm_mode)
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val_cr5 |= FSL_SAI_CR5_FBT(0);
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else
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val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
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@ -525,13 +590,28 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
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FSL_SAI_CR5_FBT_MASK, val_cr5);
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}
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if (sai->soc_data->pins > 1)
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if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) <= 1)
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regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
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FSL_SAI_CR4_FCOMB_MASK, 0);
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else
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regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
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FSL_SAI_CR4_FCOMB_MASK, FSL_SAI_CR4_FCOMB_SOFT);
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dma_params = tx ? &sai->dma_params_tx : &sai->dma_params_rx;
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dma_params->addr = sai->res->start + FSL_SAI_xDR0(tx) +
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dl_cfg[dl_cfg_idx].start_off[tx] * 0x4;
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/* Find a proper tcre setting */
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for (i = 0; i < sai->soc_data->pins; i++) {
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trce_mask = (1 << (i + 1)) - 1;
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if (hweight8(dl_cfg[dl_cfg_idx].mask[tx] & trce_mask) == pins)
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break;
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}
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regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
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FSL_SAI_CR3_TRCE_MASK,
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FSL_SAI_CR3_TRCE((1 << pins) - 1));
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FSL_SAI_CR3_TRCE((dl_cfg[dl_cfg_idx].mask[tx] & trce_mask)));
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regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
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FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
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FSL_SAI_CR4_CHMOD_MASK,
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@ -743,6 +823,23 @@ static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
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return 0;
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}
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static int fsl_sai_dai_resume(struct snd_soc_component *component)
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{
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struct fsl_sai *sai = snd_soc_component_get_drvdata(component);
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struct device *dev = &sai->pdev->dev;
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int ret;
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if (!IS_ERR_OR_NULL(sai->pinctrl) && !IS_ERR_OR_NULL(sai->pins_state)) {
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ret = pinctrl_select_state(sai->pinctrl, sai->pins_state);
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if (ret) {
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dev_err(dev, "failed to set proper pins state: %d\n", ret);
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return ret;
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}
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}
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return 0;
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}
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static struct snd_soc_dai_driver fsl_sai_dai_template = {
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.probe = fsl_sai_dai_probe,
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.playback = {
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@ -750,7 +847,7 @@ static struct snd_soc_dai_driver fsl_sai_dai_template = {
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.channels_min = 1,
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.channels_max = 32,
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.rate_min = 8000,
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.rate_max = 192000,
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.rate_max = 2822400,
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.rates = SNDRV_PCM_RATE_KNOT,
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.formats = FSL_SAI_FORMATS,
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},
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@ -759,7 +856,7 @@ static struct snd_soc_dai_driver fsl_sai_dai_template = {
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.channels_min = 1,
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.channels_max = 32,
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.rate_min = 8000,
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.rate_max = 192000,
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.rate_max = 2822400,
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.rates = SNDRV_PCM_RATE_KNOT,
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.formats = FSL_SAI_FORMATS,
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},
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@ -768,6 +865,7 @@ static struct snd_soc_dai_driver fsl_sai_dai_template = {
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static const struct snd_soc_component_driver fsl_component = {
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.name = "fsl-sai",
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.resume = fsl_sai_dai_resume,
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};
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static struct reg_default fsl_sai_reg_defaults_ofs0[] = {
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@ -1004,6 +1102,118 @@ static int fsl_sai_check_version(struct device *dev)
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return 0;
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}
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/*
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* Calculate the offset between first two datalines, don't
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* different offset in one case.
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*/
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static unsigned int fsl_sai_calc_dl_off(unsigned long dl_mask)
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{
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int fbidx, nbidx, offset;
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fbidx = find_first_bit(&dl_mask, FSL_SAI_DL_NUM);
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nbidx = find_next_bit(&dl_mask, FSL_SAI_DL_NUM, fbidx + 1);
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offset = nbidx - fbidx - 1;
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return (offset < 0 || offset >= (FSL_SAI_DL_NUM - 1) ? 0 : offset);
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}
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/*
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* read the fsl,dataline property from dts file.
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* It has 3 value for each configuration, first one means the type:
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* I2S(1) or PDM(2), second one is dataline mask for 'rx', third one is
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* dataline mask for 'tx'. for example
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*
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* fsl,dataline = <1 0xff 0xff 2 0xff 0x11>,
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*
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* It means I2S type rx mask is 0xff, tx mask is 0xff, PDM type
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* rx mask is 0xff, tx mask is 0x11 (dataline 1 and 4 enabled).
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*
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*/
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static int fsl_sai_read_dlcfg(struct fsl_sai *sai)
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{
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struct platform_device *pdev = sai->pdev;
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struct device_node *np = pdev->dev.of_node;
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struct device *dev = &pdev->dev;
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int ret, elems, i, index, num_cfg;
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char *propname = "fsl,dataline";
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struct fsl_sai_dl_cfg *cfg;
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unsigned long dl_mask;
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unsigned int soc_dl;
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u32 rx, tx, type;
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elems = of_property_count_u32_elems(np, propname);
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if (elems <= 0) {
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elems = 0;
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} else if (elems % 3) {
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dev_err(dev, "Number of elements must be divisible to 3.\n");
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return -EINVAL;
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}
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num_cfg = elems / 3;
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/* Add one more for default value */
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cfg = devm_kzalloc(&pdev->dev, (num_cfg + 1) * sizeof(*cfg), GFP_KERNEL);
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if (!cfg)
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return -ENOMEM;
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/* Consider default value "0 0xFF 0xFF" if property is missing */
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soc_dl = BIT(sai->soc_data->pins) - 1;
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cfg[0].type = FSL_SAI_DL_DEFAULT;
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cfg[0].pins[0] = sai->soc_data->pins;
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cfg[0].mask[0] = soc_dl;
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cfg[0].start_off[0] = 0;
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cfg[0].next_off[0] = 0;
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cfg[0].pins[1] = sai->soc_data->pins;
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cfg[0].mask[1] = soc_dl;
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cfg[0].start_off[1] = 0;
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cfg[0].next_off[1] = 0;
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for (i = 1, index = 0; i < num_cfg + 1; i++) {
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/*
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* type of dataline
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* 0 means default mode
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* 1 means I2S mode
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* 2 means PDM mode
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*/
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ret = of_property_read_u32_index(np, propname, index++, &type);
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if (ret)
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return -EINVAL;
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ret = of_property_read_u32_index(np, propname, index++, &rx);
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if (ret)
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return -EINVAL;
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ret = of_property_read_u32_index(np, propname, index++, &tx);
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if (ret)
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return -EINVAL;
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if ((rx & ~soc_dl) || (tx & ~soc_dl)) {
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dev_err(dev, "dataline cfg[%d] setting error, mask is 0x%x\n", i, soc_dl);
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return -EINVAL;
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}
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rx = rx & soc_dl;
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tx = tx & soc_dl;
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cfg[i].type = type;
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cfg[i].pins[0] = hweight8(rx);
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cfg[i].mask[0] = rx;
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dl_mask = rx;
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cfg[i].start_off[0] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM);
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cfg[i].next_off[0] = fsl_sai_calc_dl_off(rx);
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cfg[i].pins[1] = hweight8(tx);
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cfg[i].mask[1] = tx;
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dl_mask = tx;
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cfg[i].start_off[1] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM);
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cfg[i].next_off[1] = fsl_sai_calc_dl_off(tx);
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}
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sai->dl_cfg = cfg;
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sai->dl_cfg_cnt = num_cfg + 1;
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return 0;
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}
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static int fsl_sai_runtime_suspend(struct device *dev);
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static int fsl_sai_runtime_resume(struct device *dev);
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@ -1013,7 +1223,6 @@ static int fsl_sai_probe(struct platform_device *pdev)
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struct device *dev = &pdev->dev;
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struct fsl_sai *sai;
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struct regmap *gpr;
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struct resource *res;
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void __iomem *base;
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char tmp[8];
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int irq, ret, i;
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@ -1028,7 +1237,7 @@ static int fsl_sai_probe(struct platform_device *pdev)
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sai->is_lsb_first = of_property_read_bool(np, "lsb-first");
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base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
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base = devm_platform_get_and_ioremap_resource(pdev, 0, &sai->res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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@ -1071,6 +1280,13 @@ static int fsl_sai_probe(struct platform_device *pdev)
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else
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sai->mclk_clk[0] = sai->bus_clk;
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/* read dataline mask for rx and tx*/
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ret = fsl_sai_read_dlcfg(sai);
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if (ret < 0) {
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dev_err(dev, "failed to read dlcfg %d\n", ret);
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return ret;
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}
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
|
||||
@ -1128,11 +1344,13 @@ static int fsl_sai_probe(struct platform_device *pdev)
|
||||
MCLK_DIR(index));
|
||||
}
|
||||
|
||||
sai->dma_params_rx.addr = res->start + FSL_SAI_RDR0;
|
||||
sai->dma_params_tx.addr = res->start + FSL_SAI_TDR0;
|
||||
sai->dma_params_rx.addr = sai->res->start + FSL_SAI_RDR0;
|
||||
sai->dma_params_tx.addr = sai->res->start + FSL_SAI_TDR0;
|
||||
sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX;
|
||||
sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX;
|
||||
|
||||
sai->pinctrl = devm_pinctrl_get(&pdev->dev);
|
||||
|
||||
platform_set_drvdata(pdev, sai);
|
||||
pm_runtime_enable(dev);
|
||||
if (!pm_runtime_enabled(dev)) {
|
||||
|
||||
@ -11,7 +11,10 @@
|
||||
#define FSL_SAI_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
|
||||
SNDRV_PCM_FMTBIT_S20_3LE |\
|
||||
SNDRV_PCM_FMTBIT_S24_LE |\
|
||||
SNDRV_PCM_FMTBIT_S32_LE)
|
||||
SNDRV_PCM_FMTBIT_S32_LE |\
|
||||
SNDRV_PCM_FMTBIT_DSD_U8 |\
|
||||
SNDRV_PCM_FMTBIT_DSD_U16_LE |\
|
||||
SNDRV_PCM_FMTBIT_DSD_U32_LE)
|
||||
|
||||
/* SAI Register Map Register */
|
||||
#define FSL_SAI_VERID 0x00 /* SAI Version ID Register */
|
||||
@ -215,6 +218,13 @@
|
||||
|
||||
#define PMQOS_CPU_LATENCY BIT(0)
|
||||
|
||||
/* Max number of dataline */
|
||||
#define FSL_SAI_DL_NUM (8)
|
||||
/* default dataline type is zero */
|
||||
#define FSL_SAI_DL_DEFAULT (0)
|
||||
#define FSL_SAI_DL_I2S BIT(0)
|
||||
#define FSL_SAI_DL_PDM BIT(1)
|
||||
|
||||
struct fsl_sai_soc_data {
|
||||
bool use_imx_pcm;
|
||||
bool use_edma;
|
||||
@ -250,16 +260,28 @@ struct fsl_sai_param {
|
||||
u32 dataline;
|
||||
};
|
||||
|
||||
struct fsl_sai_dl_cfg {
|
||||
unsigned int type;
|
||||
unsigned int pins[2];
|
||||
unsigned int mask[2];
|
||||
unsigned int start_off[2];
|
||||
unsigned int next_off[2];
|
||||
};
|
||||
|
||||
struct fsl_sai {
|
||||
struct platform_device *pdev;
|
||||
struct regmap *regmap;
|
||||
struct clk *bus_clk;
|
||||
struct clk *mclk_clk[FSL_SAI_MCLK_MAX];
|
||||
struct resource *res;
|
||||
|
||||
bool is_consumer_mode;
|
||||
bool is_lsb_first;
|
||||
bool is_dsp_mode;
|
||||
bool is_pdm_mode;
|
||||
bool synchronous[2];
|
||||
struct fsl_sai_dl_cfg *dl_cfg;
|
||||
unsigned int dl_cfg_cnt;
|
||||
|
||||
unsigned int mclk_id[2];
|
||||
unsigned int mclk_streams;
|
||||
@ -274,6 +296,8 @@ struct fsl_sai {
|
||||
struct fsl_sai_verid verid;
|
||||
struct fsl_sai_param param;
|
||||
struct pm_qos_request pm_qos_req;
|
||||
struct pinctrl *pinctrl;
|
||||
struct pinctrl_state *pins_state;
|
||||
};
|
||||
|
||||
#define TX 1
|
||||
|
||||
Loading…
Reference in New Issue
Block a user