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Merge branch 'net-dsa-lantiq_gswip-code-improvements'
Martin Schiller says: ==================== net: dsa: lantiq_gswip: code improvements This patchset for the lantiq_gswip driver is a collection of minor fixes and coding improvements by Martin Blumenstingl without any real changes in the actual functionality. ==================== Link: https://lore.kernel.org/r/20240611135434.3180973-1-ms@dev.tdt.de Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski
commit
6e7e2e7e63
202
Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml
Normal file
202
Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml
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@ -0,0 +1,202 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/dsa/lantiq,gswip.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Lantiq GSWIP Ethernet switches
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allOf:
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- $ref: dsa.yaml#/$defs/ethernet-ports
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maintainers:
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- Hauke Mehrtens <hauke@hauke-m.de>
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properties:
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compatible:
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enum:
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- lantiq,xrx200-gswip
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- lantiq,xrx300-gswip
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- lantiq,xrx330-gswip
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reg:
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minItems: 3
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maxItems: 3
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reg-names:
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items:
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- const: switch
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- const: mdio
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- const: mii
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mdio:
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$ref: /schemas/net/mdio.yaml#
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unevaluatedProperties: false
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properties:
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compatible:
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const: lantiq,xrx200-mdio
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required:
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- compatible
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gphy-fw:
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type: object
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properties:
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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compatible:
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items:
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- enum:
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- lantiq,xrx200-gphy-fw
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- lantiq,xrx300-gphy-fw
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- lantiq,xrx330-gphy-fw
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- const: lantiq,gphy-fw
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lantiq,rcu:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: phandle to the RCU syscon
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patternProperties:
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"^gphy@[0-9a-f]{1,2}$":
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type: object
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additionalProperties: false
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properties:
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reg:
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minimum: 0
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maximum: 255
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description:
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Offset of the GPHY firmware register in the RCU register range
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resets:
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items:
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- description: GPHY reset line
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reset-names:
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items:
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- const: gphy
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required:
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- reg
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required:
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- compatible
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- lantiq,rcu
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additionalProperties: false
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required:
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- compatible
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- reg
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unevaluatedProperties: false
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examples:
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- |
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switch@e108000 {
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compatible = "lantiq,xrx200-gswip";
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reg = <0xe108000 0x3100>, /* switch */
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<0xe10b100 0xd8>, /* mdio */
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<0xe10b1d8 0x130>; /* mii */
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dsa,member = <0 0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan3";
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phy-mode = "rgmii";
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phy-handle = <&phy0>;
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};
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port@1 {
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reg = <1>;
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label = "lan4";
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phy-mode = "rgmii";
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phy-handle = <&phy1>;
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};
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port@2 {
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reg = <2>;
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label = "lan2";
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phy-mode = "internal";
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phy-handle = <&phy11>;
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};
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port@4 {
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reg = <4>;
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label = "lan1";
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phy-mode = "internal";
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phy-handle = <&phy13>;
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};
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port@5 {
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reg = <5>;
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label = "wan";
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phy-mode = "rgmii";
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phy-handle = <&phy5>;
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};
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port@6 {
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reg = <0x6>;
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phy-mode = "internal";
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ethernet = <ð0>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "lantiq,xrx200-mdio";
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phy0: ethernet-phy@0 {
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reg = <0x0>;
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};
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phy1: ethernet-phy@1 {
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reg = <0x1>;
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};
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phy5: ethernet-phy@5 {
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reg = <0x5>;
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};
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phy11: ethernet-phy@11 {
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reg = <0x11>;
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};
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phy13: ethernet-phy@13 {
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reg = <0x13>;
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};
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};
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gphy-fw {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "lantiq,xrx200-gphy-fw", "lantiq,gphy-fw";
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lantiq,rcu = <&rcu0>;
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gphy@20 {
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reg = <0x20>;
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resets = <&reset0 31 30>;
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reset-names = "gphy";
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};
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gphy@68 {
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reg = <0x68>;
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resets = <&reset0 29 28>;
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reset-names = "gphy";
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};
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};
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};
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@ -1,146 +0,0 @@
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Lantiq GSWIP Ethernet switches
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==================================
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Required properties for GSWIP core:
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- compatible : "lantiq,xrx200-gswip" for the embedded GSWIP in the
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xRX200 SoC
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"lantiq,xrx300-gswip" for the embedded GSWIP in the
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xRX300 SoC
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"lantiq,xrx330-gswip" for the embedded GSWIP in the
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xRX330 SoC
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- reg : memory range of the GSWIP core registers
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: memory range of the GSWIP MDIO registers
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: memory range of the GSWIP MII registers
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See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of
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additional required and optional properties.
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Required properties for MDIO bus:
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- compatible : "lantiq,xrx200-mdio" for the MDIO bus inside the GSWIP
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core of the xRX200 SoC and the PHYs connected to it.
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See Documentation/devicetree/bindings/net/mdio.txt for a list of additional
|
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required and optional properties.
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Required properties for GPHY firmware loading:
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- compatible : "lantiq,xrx200-gphy-fw", "lantiq,gphy-fw"
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"lantiq,xrx300-gphy-fw", "lantiq,gphy-fw"
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"lantiq,xrx330-gphy-fw", "lantiq,gphy-fw"
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for the loading of the firmware into the embedded
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GPHY core of the SoC.
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- lantiq,rcu : reference to the rcu syscon
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The GPHY firmware loader has a list of GPHY entries, one for each
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embedded GPHY
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- reg : Offset of the GPHY firmware register in the RCU
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register range
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- resets : list of resets of the embedded GPHY
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- reset-names : list of names of the resets
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Example:
|
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Ethernet switch on the VRX200 SoC:
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switch@e108000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "lantiq,xrx200-gswip";
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reg = < 0xe108000 0x3100 /* switch */
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0xe10b100 0xd8 /* mdio */
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0xe10b1d8 0x130 /* mii */
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>;
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dsa,member = <0 0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan3";
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phy-mode = "rgmii";
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phy-handle = <&phy0>;
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};
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port@1 {
|
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reg = <1>;
|
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label = "lan4";
|
|
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phy-mode = "rgmii";
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phy-handle = <&phy1>;
|
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};
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|
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port@2 {
|
|
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reg = <2>;
|
|
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label = "lan2";
|
|
||||||
phy-mode = "internal";
|
|
||||||
phy-handle = <&phy11>;
|
|
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};
|
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||||||
|
|
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port@4 {
|
|
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reg = <4>;
|
|
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label = "lan1";
|
|
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phy-mode = "internal";
|
|
||||||
phy-handle = <&phy13>;
|
|
||||||
};
|
|
||||||
|
|
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port@5 {
|
|
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reg = <5>;
|
|
||||||
label = "wan";
|
|
||||||
phy-mode = "rgmii";
|
|
||||||
phy-handle = <&phy5>;
|
|
||||||
};
|
|
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|
|
||||||
port@6 {
|
|
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reg = <0x6>;
|
|
||||||
ethernet = <ð0>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "lantiq,xrx200-mdio";
|
|
||||||
reg = <0>;
|
|
||||||
|
|
||||||
phy0: ethernet-phy@0 {
|
|
||||||
reg = <0x0>;
|
|
||||||
};
|
|
||||||
phy1: ethernet-phy@1 {
|
|
||||||
reg = <0x1>;
|
|
||||||
};
|
|
||||||
phy5: ethernet-phy@5 {
|
|
||||||
reg = <0x5>;
|
|
||||||
};
|
|
||||||
phy11: ethernet-phy@11 {
|
|
||||||
reg = <0x11>;
|
|
||||||
};
|
|
||||||
phy13: ethernet-phy@13 {
|
|
||||||
reg = <0x13>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
gphy-fw {
|
|
||||||
compatible = "lantiq,xrx200-gphy-fw", "lantiq,gphy-fw";
|
|
||||||
lantiq,rcu = <&rcu0>;
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
|
|
||||||
gphy@20 {
|
|
||||||
reg = <0x20>;
|
|
||||||
|
|
||||||
resets = <&reset0 31 30>;
|
|
||||||
reset-names = "gphy";
|
|
||||||
};
|
|
||||||
|
|
||||||
gphy@68 {
|
|
||||||
reg = <0x68>;
|
|
||||||
|
|
||||||
resets = <&reset0 29 28>;
|
|
||||||
reset-names = "gphy";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
@ -12449,6 +12449,7 @@ LANTIQ / INTEL Ethernet drivers
|
|||||||
M: Hauke Mehrtens <hauke@hauke-m.de>
|
M: Hauke Mehrtens <hauke@hauke-m.de>
|
||||||
L: netdev@vger.kernel.org
|
L: netdev@vger.kernel.org
|
||||||
S: Maintained
|
S: Maintained
|
||||||
|
F: Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml
|
||||||
F: drivers/net/dsa/lantiq_gswip.c
|
F: drivers/net/dsa/lantiq_gswip.c
|
||||||
F: drivers/net/dsa/lantiq_pce.h
|
F: drivers/net/dsa/lantiq_pce.h
|
||||||
F: drivers/net/ethernet/lantiq_xrx200.c
|
F: drivers/net/ethernet/lantiq_xrx200.c
|
||||||
|
|||||||
@ -236,7 +236,9 @@
|
|||||||
#define GSWIP_TABLE_ACTIVE_VLAN 0x01
|
#define GSWIP_TABLE_ACTIVE_VLAN 0x01
|
||||||
#define GSWIP_TABLE_VLAN_MAPPING 0x02
|
#define GSWIP_TABLE_VLAN_MAPPING 0x02
|
||||||
#define GSWIP_TABLE_MAC_BRIDGE 0x0b
|
#define GSWIP_TABLE_MAC_BRIDGE 0x0b
|
||||||
#define GSWIP_TABLE_MAC_BRIDGE_STATIC 0x01 /* Static not, aging entry */
|
#define GSWIP_TABLE_MAC_BRIDGE_KEY3_FID GENMASK(5, 0) /* Filtering identifier */
|
||||||
|
#define GSWIP_TABLE_MAC_BRIDGE_VAL0_PORT GENMASK(7, 4) /* Port on learned entries */
|
||||||
|
#define GSWIP_TABLE_MAC_BRIDGE_VAL1_STATIC BIT(0) /* Static, non-aging entry */
|
||||||
|
|
||||||
#define XRX200_GPHY_FW_ALIGN (16 * 1024)
|
#define XRX200_GPHY_FW_ALIGN (16 * 1024)
|
||||||
|
|
||||||
@ -653,14 +655,8 @@ static int gswip_add_single_port_br(struct gswip_priv *priv, int port, bool add)
|
|||||||
struct gswip_pce_table_entry vlan_active = {0,};
|
struct gswip_pce_table_entry vlan_active = {0,};
|
||||||
struct gswip_pce_table_entry vlan_mapping = {0,};
|
struct gswip_pce_table_entry vlan_mapping = {0,};
|
||||||
unsigned int cpu_port = priv->hw_info->cpu_port;
|
unsigned int cpu_port = priv->hw_info->cpu_port;
|
||||||
unsigned int max_ports = priv->hw_info->max_ports;
|
|
||||||
int err;
|
int err;
|
||||||
|
|
||||||
if (port >= max_ports) {
|
|
||||||
dev_err(priv->dev, "single port for %i supported\n", port);
|
|
||||||
return -EIO;
|
|
||||||
}
|
|
||||||
|
|
||||||
vlan_active.index = port + 1;
|
vlan_active.index = port + 1;
|
||||||
vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN;
|
vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN;
|
||||||
vlan_active.key[0] = 0; /* vid */
|
vlan_active.key[0] = 0; /* vid */
|
||||||
@ -695,13 +691,18 @@ static int gswip_port_enable(struct dsa_switch *ds, int port,
|
|||||||
struct gswip_priv *priv = ds->priv;
|
struct gswip_priv *priv = ds->priv;
|
||||||
int err;
|
int err;
|
||||||
|
|
||||||
if (!dsa_is_user_port(ds, port))
|
|
||||||
return 0;
|
|
||||||
|
|
||||||
if (!dsa_is_cpu_port(ds, port)) {
|
if (!dsa_is_cpu_port(ds, port)) {
|
||||||
|
u32 mdio_phy = 0;
|
||||||
|
|
||||||
err = gswip_add_single_port_br(priv, port, true);
|
err = gswip_add_single_port_br(priv, port, true);
|
||||||
if (err)
|
if (err)
|
||||||
return err;
|
return err;
|
||||||
|
|
||||||
|
if (phydev)
|
||||||
|
mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK;
|
||||||
|
|
||||||
|
gswip_mdio_mask(priv, GSWIP_MDIO_PHY_ADDR_MASK, mdio_phy,
|
||||||
|
GSWIP_MDIO_PHYp(port));
|
||||||
}
|
}
|
||||||
|
|
||||||
/* RMON Counter Enable for port */
|
/* RMON Counter Enable for port */
|
||||||
@ -714,16 +715,6 @@ static int gswip_port_enable(struct dsa_switch *ds, int port,
|
|||||||
gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN,
|
gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN,
|
||||||
GSWIP_SDMA_PCTRLp(port));
|
GSWIP_SDMA_PCTRLp(port));
|
||||||
|
|
||||||
if (!dsa_is_cpu_port(ds, port)) {
|
|
||||||
u32 mdio_phy = 0;
|
|
||||||
|
|
||||||
if (phydev)
|
|
||||||
mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK;
|
|
||||||
|
|
||||||
gswip_mdio_mask(priv, GSWIP_MDIO_PHY_ADDR_MASK, mdio_phy,
|
|
||||||
GSWIP_MDIO_PHYp(port));
|
|
||||||
}
|
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -731,9 +722,6 @@ static void gswip_port_disable(struct dsa_switch *ds, int port)
|
|||||||
{
|
{
|
||||||
struct gswip_priv *priv = ds->priv;
|
struct gswip_priv *priv = ds->priv;
|
||||||
|
|
||||||
if (!dsa_is_user_port(ds, port))
|
|
||||||
return;
|
|
||||||
|
|
||||||
gswip_switch_mask(priv, GSWIP_FDMA_PCTRL_EN, 0,
|
gswip_switch_mask(priv, GSWIP_FDMA_PCTRL_EN, 0,
|
||||||
GSWIP_FDMA_PCTRLp(port));
|
GSWIP_FDMA_PCTRLp(port));
|
||||||
gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0,
|
gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0,
|
||||||
@ -792,7 +780,7 @@ static int gswip_port_vlan_filtering(struct dsa_switch *ds, int port,
|
|||||||
}
|
}
|
||||||
|
|
||||||
if (vlan_filtering) {
|
if (vlan_filtering) {
|
||||||
/* Use port based VLAN tag */
|
/* Use tag based VLAN */
|
||||||
gswip_switch_mask(priv,
|
gswip_switch_mask(priv,
|
||||||
GSWIP_PCE_VCTRL_VSR,
|
GSWIP_PCE_VCTRL_VSR,
|
||||||
GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR |
|
GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR |
|
||||||
@ -801,7 +789,7 @@ static int gswip_port_vlan_filtering(struct dsa_switch *ds, int port,
|
|||||||
gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_TVM, 0,
|
gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_TVM, 0,
|
||||||
GSWIP_PCE_PCTRL_0p(port));
|
GSWIP_PCE_PCTRL_0p(port));
|
||||||
} else {
|
} else {
|
||||||
/* Use port based VLAN tag */
|
/* Use port based VLAN */
|
||||||
gswip_switch_mask(priv,
|
gswip_switch_mask(priv,
|
||||||
GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR |
|
GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR |
|
||||||
GSWIP_PCE_VCTRL_VEMR,
|
GSWIP_PCE_VCTRL_VEMR,
|
||||||
@ -836,7 +824,7 @@ static int gswip_setup(struct dsa_switch *ds)
|
|||||||
|
|
||||||
err = gswip_pce_load_microcode(priv);
|
err = gswip_pce_load_microcode(priv);
|
||||||
if (err) {
|
if (err) {
|
||||||
dev_err(priv->dev, "writing PCE microcode failed, %i", err);
|
dev_err(priv->dev, "writing PCE microcode failed, %i\n", err);
|
||||||
return err;
|
return err;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -898,8 +886,6 @@ static int gswip_setup(struct dsa_switch *ds)
|
|||||||
|
|
||||||
ds->mtu_enforcement_ingress = true;
|
ds->mtu_enforcement_ingress = true;
|
||||||
|
|
||||||
gswip_port_enable(ds, cpu_port, NULL);
|
|
||||||
|
|
||||||
ds->configure_vlan_while_not_filtering = false;
|
ds->configure_vlan_while_not_filtering = false;
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
@ -1314,10 +1300,11 @@ static void gswip_port_fast_age(struct dsa_switch *ds, int port)
|
|||||||
if (!mac_bridge.valid)
|
if (!mac_bridge.valid)
|
||||||
continue;
|
continue;
|
||||||
|
|
||||||
if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC)
|
if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_VAL1_STATIC)
|
||||||
continue;
|
continue;
|
||||||
|
|
||||||
if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) != port)
|
if (port != FIELD_GET(GSWIP_TABLE_MAC_BRIDGE_VAL0_PORT,
|
||||||
|
mac_bridge.val[0]))
|
||||||
continue;
|
continue;
|
||||||
|
|
||||||
mac_bridge.valid = false;
|
mac_bridge.valid = false;
|
||||||
@ -1383,7 +1370,8 @@ static int gswip_port_fdb(struct dsa_switch *ds, int port,
|
|||||||
}
|
}
|
||||||
|
|
||||||
if (fid == -1) {
|
if (fid == -1) {
|
||||||
dev_err(priv->dev, "Port not part of a bridge\n");
|
dev_err(priv->dev, "no FID found for bridge %s\n",
|
||||||
|
bridge->name);
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -1392,9 +1380,9 @@ static int gswip_port_fdb(struct dsa_switch *ds, int port,
|
|||||||
mac_bridge.key[0] = addr[5] | (addr[4] << 8);
|
mac_bridge.key[0] = addr[5] | (addr[4] << 8);
|
||||||
mac_bridge.key[1] = addr[3] | (addr[2] << 8);
|
mac_bridge.key[1] = addr[3] | (addr[2] << 8);
|
||||||
mac_bridge.key[2] = addr[1] | (addr[0] << 8);
|
mac_bridge.key[2] = addr[1] | (addr[0] << 8);
|
||||||
mac_bridge.key[3] = fid;
|
mac_bridge.key[3] = FIELD_PREP(GSWIP_TABLE_MAC_BRIDGE_KEY3_FID, fid);
|
||||||
mac_bridge.val[0] = add ? BIT(port) : 0; /* port map */
|
mac_bridge.val[0] = add ? BIT(port) : 0; /* port map */
|
||||||
mac_bridge.val[1] = GSWIP_TABLE_MAC_BRIDGE_STATIC;
|
mac_bridge.val[1] = GSWIP_TABLE_MAC_BRIDGE_VAL1_STATIC;
|
||||||
mac_bridge.valid = add;
|
mac_bridge.valid = add;
|
||||||
|
|
||||||
err = gswip_pce_table_entry_write(priv, &mac_bridge);
|
err = gswip_pce_table_entry_write(priv, &mac_bridge);
|
||||||
@ -1423,7 +1411,7 @@ static int gswip_port_fdb_dump(struct dsa_switch *ds, int port,
|
|||||||
{
|
{
|
||||||
struct gswip_priv *priv = ds->priv;
|
struct gswip_priv *priv = ds->priv;
|
||||||
struct gswip_pce_table_entry mac_bridge = {0,};
|
struct gswip_pce_table_entry mac_bridge = {0,};
|
||||||
unsigned char addr[6];
|
unsigned char addr[ETH_ALEN];
|
||||||
int i;
|
int i;
|
||||||
int err;
|
int err;
|
||||||
|
|
||||||
@ -1448,14 +1436,15 @@ static int gswip_port_fdb_dump(struct dsa_switch *ds, int port,
|
|||||||
addr[2] = (mac_bridge.key[1] >> 8) & 0xff;
|
addr[2] = (mac_bridge.key[1] >> 8) & 0xff;
|
||||||
addr[1] = mac_bridge.key[2] & 0xff;
|
addr[1] = mac_bridge.key[2] & 0xff;
|
||||||
addr[0] = (mac_bridge.key[2] >> 8) & 0xff;
|
addr[0] = (mac_bridge.key[2] >> 8) & 0xff;
|
||||||
if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC) {
|
if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_VAL1_STATIC) {
|
||||||
if (mac_bridge.val[0] & BIT(port)) {
|
if (mac_bridge.val[0] & BIT(port)) {
|
||||||
err = cb(addr, 0, true, data);
|
err = cb(addr, 0, true, data);
|
||||||
if (err)
|
if (err)
|
||||||
return err;
|
return err;
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) == port) {
|
if (port == FIELD_GET(GSWIP_TABLE_MAC_BRIDGE_VAL0_PORT,
|
||||||
|
mac_bridge.val[0])) {
|
||||||
err = cb(addr, 0, false, data);
|
err = cb(addr, 0, false, data);
|
||||||
if (err)
|
if (err)
|
||||||
return err;
|
return err;
|
||||||
@ -1474,12 +1463,11 @@ static int gswip_port_max_mtu(struct dsa_switch *ds, int port)
|
|||||||
static int gswip_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
|
static int gswip_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
|
||||||
{
|
{
|
||||||
struct gswip_priv *priv = ds->priv;
|
struct gswip_priv *priv = ds->priv;
|
||||||
int cpu_port = priv->hw_info->cpu_port;
|
|
||||||
|
|
||||||
/* CPU port always has maximum mtu of user ports, so use it to set
|
/* CPU port always has maximum mtu of user ports, so use it to set
|
||||||
* switch frame size, including 8 byte special header.
|
* switch frame size, including 8 byte special header.
|
||||||
*/
|
*/
|
||||||
if (port == cpu_port) {
|
if (dsa_is_cpu_port(ds, port)) {
|
||||||
new_mtu += 8;
|
new_mtu += 8;
|
||||||
gswip_switch_w(priv, VLAN_ETH_HLEN + new_mtu + ETH_FCS_LEN,
|
gswip_switch_w(priv, VLAN_ETH_HLEN + new_mtu + ETH_FCS_LEN,
|
||||||
GSWIP_MAC_FLEN);
|
GSWIP_MAC_FLEN);
|
||||||
@ -1516,6 +1504,7 @@ static void gswip_xrx200_phylink_get_caps(struct dsa_switch *ds, int port,
|
|||||||
case 2:
|
case 2:
|
||||||
case 3:
|
case 3:
|
||||||
case 4:
|
case 4:
|
||||||
|
case 6:
|
||||||
__set_bit(PHY_INTERFACE_MODE_INTERNAL,
|
__set_bit(PHY_INTERFACE_MODE_INTERNAL,
|
||||||
config->supported_interfaces);
|
config->supported_interfaces);
|
||||||
break;
|
break;
|
||||||
@ -1547,6 +1536,7 @@ static void gswip_xrx300_phylink_get_caps(struct dsa_switch *ds, int port,
|
|||||||
case 2:
|
case 2:
|
||||||
case 3:
|
case 3:
|
||||||
case 4:
|
case 4:
|
||||||
|
case 6:
|
||||||
__set_bit(PHY_INTERFACE_MODE_INTERNAL,
|
__set_bit(PHY_INTERFACE_MODE_INTERNAL,
|
||||||
config->supported_interfaces);
|
config->supported_interfaces);
|
||||||
break;
|
break;
|
||||||
@ -1790,7 +1780,7 @@ static u32 gswip_bcm_ram_entry_read(struct gswip_priv *priv, u32 table,
|
|||||||
err = gswip_switch_r_timeout(priv, GSWIP_BM_RAM_CTRL,
|
err = gswip_switch_r_timeout(priv, GSWIP_BM_RAM_CTRL,
|
||||||
GSWIP_BM_RAM_CTRL_BAS);
|
GSWIP_BM_RAM_CTRL_BAS);
|
||||||
if (err) {
|
if (err) {
|
||||||
dev_err(priv->dev, "timeout while reading table: %u, index: %u",
|
dev_err(priv->dev, "timeout while reading table: %u, index: %u\n",
|
||||||
table, index);
|
table, index);
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
@ -1929,11 +1919,9 @@ static int gswip_gphy_fw_load(struct gswip_priv *priv, struct gswip_gphy_fw *gph
|
|||||||
msleep(200);
|
msleep(200);
|
||||||
|
|
||||||
ret = request_firmware(&fw, gphy_fw->fw_name, dev);
|
ret = request_firmware(&fw, gphy_fw->fw_name, dev);
|
||||||
if (ret) {
|
if (ret)
|
||||||
dev_err(dev, "failed to load firmware: %s, error: %i\n",
|
return dev_err_probe(dev, ret, "failed to load firmware: %s\n",
|
||||||
gphy_fw->fw_name, ret);
|
gphy_fw->fw_name);
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* GPHY cores need the firmware code in a persistent and contiguous
|
/* GPHY cores need the firmware code in a persistent and contiguous
|
||||||
* memory area with a 16 kB boundary aligned start address.
|
* memory area with a 16 kB boundary aligned start address.
|
||||||
@ -1946,9 +1934,9 @@ static int gswip_gphy_fw_load(struct gswip_priv *priv, struct gswip_gphy_fw *gph
|
|||||||
dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN);
|
dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN);
|
||||||
memcpy(fw_addr, fw->data, fw->size);
|
memcpy(fw_addr, fw->data, fw->size);
|
||||||
} else {
|
} else {
|
||||||
dev_err(dev, "failed to alloc firmware memory\n");
|
|
||||||
release_firmware(fw);
|
release_firmware(fw);
|
||||||
return -ENOMEM;
|
return dev_err_probe(dev, -ENOMEM,
|
||||||
|
"failed to alloc firmware memory\n");
|
||||||
}
|
}
|
||||||
|
|
||||||
release_firmware(fw);
|
release_firmware(fw);
|
||||||
@ -1975,8 +1963,8 @@ static int gswip_gphy_fw_probe(struct gswip_priv *priv,
|
|||||||
|
|
||||||
gphy_fw->clk_gate = devm_clk_get(dev, gphyname);
|
gphy_fw->clk_gate = devm_clk_get(dev, gphyname);
|
||||||
if (IS_ERR(gphy_fw->clk_gate)) {
|
if (IS_ERR(gphy_fw->clk_gate)) {
|
||||||
dev_err(dev, "Failed to lookup gate clock\n");
|
return dev_err_probe(dev, PTR_ERR(gphy_fw->clk_gate),
|
||||||
return PTR_ERR(gphy_fw->clk_gate);
|
"Failed to lookup gate clock\n");
|
||||||
}
|
}
|
||||||
|
|
||||||
ret = of_property_read_u32(gphy_fw_np, "reg", &gphy_fw->fw_addr_offset);
|
ret = of_property_read_u32(gphy_fw_np, "reg", &gphy_fw->fw_addr_offset);
|
||||||
@ -1996,8 +1984,8 @@ static int gswip_gphy_fw_probe(struct gswip_priv *priv,
|
|||||||
gphy_fw->fw_name = priv->gphy_fw_name_cfg->ge_firmware_name;
|
gphy_fw->fw_name = priv->gphy_fw_name_cfg->ge_firmware_name;
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode);
|
return dev_err_probe(dev, -EINVAL, "Unknown GPHY mode %d\n",
|
||||||
return -EINVAL;
|
gphy_mode);
|
||||||
}
|
}
|
||||||
|
|
||||||
gphy_fw->reset = of_reset_control_array_get_exclusive(gphy_fw_np);
|
gphy_fw->reset = of_reset_control_array_get_exclusive(gphy_fw_np);
|
||||||
@ -2019,7 +2007,7 @@ static void gswip_gphy_fw_remove(struct gswip_priv *priv,
|
|||||||
|
|
||||||
ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, 0);
|
ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, 0);
|
||||||
if (ret)
|
if (ret)
|
||||||
dev_err(priv->dev, "can not reset GPHY FW pointer");
|
dev_err(priv->dev, "can not reset GPHY FW pointer\n");
|
||||||
|
|
||||||
clk_disable_unprepare(gphy_fw->clk_gate);
|
clk_disable_unprepare(gphy_fw->clk_gate);
|
||||||
|
|
||||||
@ -2048,8 +2036,9 @@ static int gswip_gphy_fw_list(struct gswip_priv *priv,
|
|||||||
priv->gphy_fw_name_cfg = &xrx200a2x_gphy_data;
|
priv->gphy_fw_name_cfg = &xrx200a2x_gphy_data;
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
dev_err(dev, "unknown GSWIP version: 0x%x", version);
|
return dev_err_probe(dev, -ENOENT,
|
||||||
return -ENOENT;
|
"unknown GSWIP version: 0x%x\n",
|
||||||
|
version);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -2057,10 +2046,9 @@ static int gswip_gphy_fw_list(struct gswip_priv *priv,
|
|||||||
if (match && match->data)
|
if (match && match->data)
|
||||||
priv->gphy_fw_name_cfg = match->data;
|
priv->gphy_fw_name_cfg = match->data;
|
||||||
|
|
||||||
if (!priv->gphy_fw_name_cfg) {
|
if (!priv->gphy_fw_name_cfg)
|
||||||
dev_err(dev, "GPHY compatible type not supported");
|
return dev_err_probe(dev, -ENOENT,
|
||||||
return -ENOENT;
|
"GPHY compatible type not supported\n");
|
||||||
}
|
|
||||||
|
|
||||||
priv->num_gphy_fw = of_get_available_child_count(gphy_fw_list_np);
|
priv->num_gphy_fw = of_get_available_child_count(gphy_fw_list_np);
|
||||||
if (!priv->num_gphy_fw)
|
if (!priv->num_gphy_fw)
|
||||||
@ -2161,8 +2149,8 @@ static int gswip_probe(struct platform_device *pdev)
|
|||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
dev_err(dev, "unknown GSWIP version: 0x%x", version);
|
return dev_err_probe(dev, -ENOENT,
|
||||||
return -ENOENT;
|
"unknown GSWIP version: 0x%x\n", version);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* bring up the mdio bus */
|
/* bring up the mdio bus */
|
||||||
@ -2170,28 +2158,27 @@ static int gswip_probe(struct platform_device *pdev)
|
|||||||
if (gphy_fw_np) {
|
if (gphy_fw_np) {
|
||||||
err = gswip_gphy_fw_list(priv, gphy_fw_np, version);
|
err = gswip_gphy_fw_list(priv, gphy_fw_np, version);
|
||||||
of_node_put(gphy_fw_np);
|
of_node_put(gphy_fw_np);
|
||||||
if (err) {
|
if (err)
|
||||||
dev_err(dev, "gphy fw probe failed\n");
|
return dev_err_probe(dev, err,
|
||||||
return err;
|
"gphy fw probe failed\n");
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/* bring up the mdio bus */
|
/* bring up the mdio bus */
|
||||||
err = gswip_mdio(priv);
|
err = gswip_mdio(priv);
|
||||||
if (err) {
|
if (err) {
|
||||||
dev_err(dev, "mdio probe failed\n");
|
dev_err_probe(dev, err, "mdio probe failed\n");
|
||||||
goto gphy_fw_remove;
|
goto gphy_fw_remove;
|
||||||
}
|
}
|
||||||
|
|
||||||
err = dsa_register_switch(priv->ds);
|
err = dsa_register_switch(priv->ds);
|
||||||
if (err) {
|
if (err) {
|
||||||
dev_err(dev, "dsa switch register failed: %i\n", err);
|
dev_err_probe(dev, err, "dsa switch registration failed\n");
|
||||||
goto gphy_fw_remove;
|
goto gphy_fw_remove;
|
||||||
}
|
}
|
||||||
if (!dsa_is_cpu_port(priv->ds, priv->hw_info->cpu_port)) {
|
if (!dsa_is_cpu_port(priv->ds, priv->hw_info->cpu_port)) {
|
||||||
dev_err(dev, "wrong CPU port defined, HW only supports port: %i",
|
err = dev_err_probe(dev, -EINVAL,
|
||||||
priv->hw_info->cpu_port);
|
"wrong CPU port defined, HW only supports port: %i\n",
|
||||||
err = -EINVAL;
|
priv->hw_info->cpu_port);
|
||||||
goto disable_switch;
|
goto disable_switch;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user