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kvm/ppc/mpic: remove some obviously unneeded code
Remove some parts of the code that are obviously QEMU or Raven specific before fixing style issues, to reduce the style issues that need to be fixed. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Scott Wood
Alexander Graf
parent
b823f98f89
commit
6dd830a09a
@ -22,39 +22,6 @@
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/*
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*
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* Based on OpenPic implementations:
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* - Intel GW80314 I/O companion chip developer's manual
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* - Motorola MPC8245 & MPC8540 user manuals.
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* - Motorola MCP750 (aka Raven) programmer manual.
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* - Motorola Harrier programmer manuel
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*
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* Serial interrupts, as implemented in Raven chipset are not supported yet.
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*
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*/
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#include "hw.h"
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#include "ppc/mac.h"
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#include "pci/pci.h"
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#include "openpic.h"
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#include "sysbus.h"
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#include "pci/msi.h"
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#include "qemu/bitops.h"
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#include "ppc.h"
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//#define DEBUG_OPENPIC
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#ifdef DEBUG_OPENPIC
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static const int debug_openpic = 1;
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#else
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static const int debug_openpic = 0;
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#endif
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#define DPRINTF(fmt, ...) do { \
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if (debug_openpic) { \
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printf(fmt , ## __VA_ARGS__); \
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} \
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} while (0)
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#define MAX_CPU 32
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#define MAX_SRC 256
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@ -82,21 +49,6 @@ static const int debug_openpic = 0;
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#define OPENPIC_CPU_REG_START 0x20000
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#define OPENPIC_CPU_REG_SIZE 0x100 + ((MAX_CPU - 1) * 0x1000)
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/* Raven */
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#define RAVEN_MAX_CPU 2
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#define RAVEN_MAX_EXT 48
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#define RAVEN_MAX_IRQ 64
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#define RAVEN_MAX_TMR MAX_TMR
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#define RAVEN_MAX_IPI MAX_IPI
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/* Interrupt definitions */
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#define RAVEN_FE_IRQ (RAVEN_MAX_EXT) /* Internal functional IRQ */
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#define RAVEN_ERR_IRQ (RAVEN_MAX_EXT + 1) /* Error IRQ */
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#define RAVEN_TMR_IRQ (RAVEN_MAX_EXT + 2) /* First timer IRQ */
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#define RAVEN_IPI_IRQ (RAVEN_TMR_IRQ + RAVEN_MAX_TMR) /* First IPI IRQ */
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/* First doorbell IRQ */
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#define RAVEN_DBL_IRQ (RAVEN_IPI_IRQ + (RAVEN_MAX_CPU * RAVEN_MAX_IPI))
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typedef struct FslMpicInfo {
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int max_ext;
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} FslMpicInfo;
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@ -138,44 +90,6 @@ static FslMpicInfo fsl_mpic_42 = {
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#define ILR_INTTGT_CINT 0x01 /* critical */
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#define ILR_INTTGT_MCP 0x02 /* machine check */
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/* The currently supported INTTGT values happen to be the same as QEMU's
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* openpic output codes, but don't depend on this. The output codes
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* could change (unlikely, but...) or support could be added for
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* more INTTGT values.
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*/
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static const int inttgt_output[][2] = {
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{ILR_INTTGT_INT, OPENPIC_OUTPUT_INT},
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{ILR_INTTGT_CINT, OPENPIC_OUTPUT_CINT},
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{ILR_INTTGT_MCP, OPENPIC_OUTPUT_MCK},
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};
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static int inttgt_to_output(int inttgt)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(inttgt_output); i++) {
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if (inttgt_output[i][0] == inttgt) {
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return inttgt_output[i][1];
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}
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}
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fprintf(stderr, "%s: unsupported inttgt %d\n", __func__, inttgt);
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return OPENPIC_OUTPUT_INT;
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}
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static int output_to_inttgt(int output)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(inttgt_output); i++) {
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if (inttgt_output[i][1] == output) {
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return inttgt_output[i][0];
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}
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}
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abort();
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}
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#define MSIIR_OFFSET 0x140
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#define MSIIR_SRS_SHIFT 29
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#define MSIIR_SRS_MASK (0x7 << MSIIR_SRS_SHIFT)
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@ -1265,228 +1179,36 @@ static uint64_t openpic_cpu_read(void *opaque, hwaddr addr, unsigned len)
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return openpic_cpu_read_internal(opaque, addr, (addr & 0x1f000) >> 12);
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}
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static const MemoryRegionOps openpic_glb_ops_le = {
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.write = openpic_gbl_write,
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.read = openpic_gbl_read,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static const MemoryRegionOps openpic_glb_ops_be = {
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.write = openpic_gbl_write,
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.read = openpic_gbl_read,
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.endianness = DEVICE_BIG_ENDIAN,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static const MemoryRegionOps openpic_tmr_ops_le = {
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.write = openpic_tmr_write,
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.read = openpic_tmr_read,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static const MemoryRegionOps openpic_tmr_ops_be = {
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.write = openpic_tmr_write,
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.read = openpic_tmr_read,
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.endianness = DEVICE_BIG_ENDIAN,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static const MemoryRegionOps openpic_cpu_ops_le = {
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.write = openpic_cpu_write,
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.read = openpic_cpu_read,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static const MemoryRegionOps openpic_cpu_ops_be = {
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.write = openpic_cpu_write,
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.read = openpic_cpu_read,
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.endianness = DEVICE_BIG_ENDIAN,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static const MemoryRegionOps openpic_src_ops_le = {
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.write = openpic_src_write,
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.read = openpic_src_read,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static const MemoryRegionOps openpic_src_ops_be = {
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.write = openpic_src_write,
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.read = openpic_src_read,
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.endianness = DEVICE_BIG_ENDIAN,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static const MemoryRegionOps openpic_msi_ops_be = {
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.read = openpic_msi_read,
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.write = openpic_msi_write,
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.endianness = DEVICE_BIG_ENDIAN,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static const MemoryRegionOps openpic_summary_ops_be = {
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.read = openpic_summary_read,
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.write = openpic_summary_write,
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.endianness = DEVICE_BIG_ENDIAN,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static void openpic_save_IRQ_queue(QEMUFile * f, IRQQueue * q)
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{
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(q->queue); i++) {
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/* Always put the lower half of a 64-bit long first, in case we
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* restore on a 32-bit host. The least significant bits correspond
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* to lower IRQ numbers in the bitmap.
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*/
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qemu_put_be32(f, (uint32_t) q->queue[i]);
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#if LONG_MAX > 0x7FFFFFFF
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qemu_put_be32(f, (uint32_t) (q->queue[i] >> 32));
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#endif
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}
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qemu_put_sbe32s(f, &q->next);
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qemu_put_sbe32s(f, &q->priority);
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}
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static void openpic_save(QEMUFile * f, void *opaque)
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{
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OpenPICState *opp = (OpenPICState *) opaque;
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unsigned int i;
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qemu_put_be32s(f, &opp->gcr);
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qemu_put_be32s(f, &opp->vir);
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qemu_put_be32s(f, &opp->pir);
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qemu_put_be32s(f, &opp->spve);
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qemu_put_be32s(f, &opp->tfrr);
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qemu_put_be32s(f, &opp->nb_cpus);
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for (i = 0; i < opp->nb_cpus; i++) {
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qemu_put_sbe32s(f, &opp->dst[i].ctpr);
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openpic_save_IRQ_queue(f, &opp->dst[i].raised);
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openpic_save_IRQ_queue(f, &opp->dst[i].servicing);
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qemu_put_buffer(f, (uint8_t *) & opp->dst[i].outputs_active,
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sizeof(opp->dst[i].outputs_active));
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}
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for (i = 0; i < MAX_TMR; i++) {
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qemu_put_be32s(f, &opp->timers[i].tccr);
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qemu_put_be32s(f, &opp->timers[i].tbcr);
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}
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for (i = 0; i < opp->max_irq; i++) {
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qemu_put_be32s(f, &opp->src[i].ivpr);
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qemu_put_be32s(f, &opp->src[i].idr);
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qemu_get_be32s(f, &opp->src[i].destmask);
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qemu_put_sbe32s(f, &opp->src[i].last_cpu);
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qemu_put_sbe32s(f, &opp->src[i].pending);
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}
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}
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static void openpic_load_IRQ_queue(QEMUFile * f, IRQQueue * q)
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{
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(q->queue); i++) {
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unsigned long val;
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val = qemu_get_be32(f);
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#if LONG_MAX > 0x7FFFFFFF
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val <<= 32;
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val |= qemu_get_be32(f);
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#endif
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q->queue[i] = val;
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}
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qemu_get_sbe32s(f, &q->next);
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qemu_get_sbe32s(f, &q->priority);
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}
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static int openpic_load(QEMUFile * f, void *opaque, int version_id)
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{
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OpenPICState *opp = (OpenPICState *) opaque;
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unsigned int i;
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if (version_id != 1) {
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return -EINVAL;
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}
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qemu_get_be32s(f, &opp->gcr);
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qemu_get_be32s(f, &opp->vir);
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qemu_get_be32s(f, &opp->pir);
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qemu_get_be32s(f, &opp->spve);
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qemu_get_be32s(f, &opp->tfrr);
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qemu_get_be32s(f, &opp->nb_cpus);
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for (i = 0; i < opp->nb_cpus; i++) {
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qemu_get_sbe32s(f, &opp->dst[i].ctpr);
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openpic_load_IRQ_queue(f, &opp->dst[i].raised);
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openpic_load_IRQ_queue(f, &opp->dst[i].servicing);
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qemu_get_buffer(f, (uint8_t *) & opp->dst[i].outputs_active,
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sizeof(opp->dst[i].outputs_active));
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}
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for (i = 0; i < MAX_TMR; i++) {
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qemu_get_be32s(f, &opp->timers[i].tccr);
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qemu_get_be32s(f, &opp->timers[i].tbcr);
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}
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for (i = 0; i < opp->max_irq; i++) {
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uint32_t val;
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val = qemu_get_be32(f);
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write_IRQreg_idr(opp, i, val);
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val = qemu_get_be32(f);
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write_IRQreg_ivpr(opp, i, val);
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qemu_get_be32s(f, &opp->src[i].ivpr);
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qemu_get_be32s(f, &opp->src[i].idr);
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qemu_get_be32s(f, &opp->src[i].destmask);
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qemu_get_sbe32s(f, &opp->src[i].last_cpu);
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qemu_get_sbe32s(f, &opp->src[i].pending);
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}
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return 0;
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}
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typedef struct MemReg {
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const char *name;
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MemoryRegionOps const *ops;
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@ -1614,73 +1336,7 @@ static int openpic_init(SysBusDevice * dev)
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map_list(opp, list_fsl, &list_count);
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break;
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case OPENPIC_MODEL_RAVEN:
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opp->nb_irqs = RAVEN_MAX_EXT;
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opp->vid = VID_REVISION_1_3;
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opp->vir = VIR_GENERIC;
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opp->vector_mask = 0xFF;
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opp->tfrr_reset = 4160000;
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opp->ivpr_reset = IVPR_MASK_MASK | IVPR_MODE_MASK;
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opp->idr_reset = 0;
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opp->max_irq = RAVEN_MAX_IRQ;
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opp->irq_ipi0 = RAVEN_IPI_IRQ;
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opp->irq_tim0 = RAVEN_TMR_IRQ;
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opp->brr1 = -1;
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opp->mpic_mode_mask = GCR_MODE_MIXED;
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/* Only UP supported today */
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if (opp->nb_cpus != 1) {
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return -EINVAL;
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}
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map_list(opp, list_le, &list_count);
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break;
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}
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for (i = 0; i < opp->nb_cpus; i++) {
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opp->dst[i].irqs = g_new(qemu_irq, OPENPIC_OUTPUT_NB);
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for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
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sysbus_init_irq(dev, &opp->dst[i].irqs[j]);
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}
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}
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register_savevm(&opp->busdev.qdev, "openpic", 0, 2,
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openpic_save, openpic_load, opp);
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sysbus_init_mmio(dev, &opp->mem);
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qdev_init_gpio_in(&dev->qdev, openpic_set_irq, opp->max_irq);
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return 0;
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}
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static Property openpic_properties[] = {
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DEFINE_PROP_UINT32("model", OpenPICState, model,
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OPENPIC_MODEL_FSL_MPIC_20),
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DEFINE_PROP_UINT32("nb_cpus", OpenPICState, nb_cpus, 1),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void openpic_class_init(ObjectClass * klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
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k->init = openpic_init;
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dc->props = openpic_properties;
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dc->reset = openpic_reset;
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}
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static const TypeInfo openpic_info = {
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.name = "openpic",
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(OpenPICState),
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.class_init = openpic_class_init,
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};
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static void openpic_register_types(void)
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{
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type_register_static(&openpic_info);
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}
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type_init(openpic_register_types)
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