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arm64: dts: realtek: rtd129x: Introduce r-bus

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Model Realtek's register bus in DT.

Signed-off-by: Andreas Färber <afaerber@suse.de>
This commit is contained in:
Andreas Färber 2019-11-10 01:17:29 +01:00
parent 690677c22d
commit 6d2fdb2410
1 changed files with 64 additions and 56 deletions
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120
arch/arm64/boot/dts/realtek/rtd129x.dtsi
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@ -55,70 +55,78 @@
/* Exclude up to 2 GiB of RAM */
ranges = <0x80000000 0x80000000 0x80000000>;
reset1: reset-controller@98000000 {
compatible = "snps,dw-low-reset";
reg = <0x98000000 0x4>;
#reset-cells = <1>;
};
rbus: bus@98000000 {
compatible = "simple-bus";
reg = <0x98000000 0x200000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x98000000 0x200000>;
reset2: reset-controller@98000004 {
compatible = "snps,dw-low-reset";
reg = <0x98000004 0x4>;
#reset-cells = <1>;
};
reset1: reset-controller@0 {
compatible = "snps,dw-low-reset";
reg = <0x0 0x4>;
#reset-cells = <1>;
};
reset3: reset-controller@98000008 {
compatible = "snps,dw-low-reset";
reg = <0x98000008 0x4>;
#reset-cells = <1>;
};
reset2: reset-controller@4 {
compatible = "snps,dw-low-reset";
reg = <0x4 0x4>;
#reset-cells = <1>;
};
reset4: reset-controller@98000050 {
compatible = "snps,dw-low-reset";
reg = <0x98000050 0x4>;
#reset-cells = <1>;
};
reset3: reset-controller@8 {
compatible = "snps,dw-low-reset";
reg = <0x8 0x4>;
#reset-cells = <1>;
};
iso_reset: reset-controller@98007088 {
compatible = "snps,dw-low-reset";
reg = <0x98007088 0x4>;
#reset-cells = <1>;
};
reset4: reset-controller@50 {
compatible = "snps,dw-low-reset";
reg = <0x50 0x4>;
#reset-cells = <1>;
};
wdt: watchdog@98007680 {
compatible = "realtek,rtd1295-watchdog";
reg = <0x98007680 0x100>;
clocks = <&osc27M>;
};
iso_reset: reset-controller@7088 {
compatible = "snps,dw-low-reset";
reg = <0x7088 0x4>;
#reset-cells = <1>;
};
uart0: serial@98007800 {
compatible = "snps,dw-apb-uart";
reg = <0x98007800 0x400>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <27000000>;
resets = <&iso_reset RTD1295_ISO_RSTN_UR0>;
status = "disabled";
};
wdt: watchdog@7680 {
compatible = "realtek,rtd1295-watchdog";
reg = <0x7680 0x100>;
clocks = <&osc27M>;
};
uart1: serial@9801b200 {
compatible = "snps,dw-apb-uart";
reg = <0x9801b200 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <432000000>;
resets = <&reset2 RTD1295_RSTN_UR1>;
status = "disabled";
};
uart0: serial@7800 {
compatible = "snps,dw-apb-uart";
reg = <0x7800 0x400>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <27000000>;
resets = <&iso_reset RTD1295_ISO_RSTN_UR0>;
status = "disabled";
};
uart2: serial@9801b400 {
compatible = "snps,dw-apb-uart";
reg = <0x9801b400 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <432000000>;
resets = <&reset2 RTD1295_RSTN_UR2>;
status = "disabled";
uart1: serial@1b200 {
compatible = "snps,dw-apb-uart";
reg = <0x1b200 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <432000000>;
resets = <&reset2 RTD1295_RSTN_UR1>;
status = "disabled";
};
uart2: serial@1b400 {
compatible = "snps,dw-apb-uart";
reg = <0x1b400 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <432000000>;
resets = <&reset2 RTD1295_RSTN_UR2>;
status = "disabled";
};
};
gic: interrupt-controller@ff011000 {