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drm/panel: ltk050h3146w: Set burst mode for ltk050h3148w
The ltk050h3148w variant expects the horizontal component lane byte clock cycle(lbcc) to be calculated using lane_mbps (burst mode) instead of the pixel clock. Using the pixel clock rate by default for this calculation was introduced in commitac87d23694
("drm/bridge: synopsys: dw-mipi-dsi: Use pixel clock rate to calculate lbcc") and starting from commit93e82bb4de
("drm/bridge: synopsys: dw-mipi-dsi: Fix hcomponent lbcc for burst mode") only panels that support burst mode can keep using the lane_mbps. So add MIPI_DSI_MODE_VIDEO_BURST as part of the mode_flags for the dsi host. Fixes:93e82bb4de
("drm/bridge: synopsys: dw-mipi-dsi: Fix hcomponent lbcc for burst mode") Signed-off-by: Farouk Bouabid <farouk.bouabid@theobroma-systems.com> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20231213145045.41020-1-farouk.bouabid@theobroma-systems.com
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@ -326,7 +326,7 @@ static const struct drm_display_mode ltk050h3148w_mode = {
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static const struct ltk050h3146w_desc ltk050h3148w_data = {
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.mode = <k050h3148w_mode,
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.init = ltk050h3148w_init_sequence,
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.mode_flags = MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
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.mode_flags = MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_MODE_VIDEO_BURST,
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};
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static int ltk050h3146w_init_sequence(struct ltk050h3146w *ctx)
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