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soc: mediatek: SVS: add monitor mode
SVS monitor mode is based on different thermal temperature to provide suitable SVS bank voltages. Signed-off-by: Roger Lu <roger.lu@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20220516004311.18358-5-roger.lu@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Roger Lu
Matthias Brugger
parent
681a02e950
commit
6c69271926
@ -25,6 +25,7 @@
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#include <linux/regulator/consumer.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/thermal.h>
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/* svs bank 1-line software id */
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#define SVSB_CPU_LITTLE BIT(0)
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@ -36,6 +37,7 @@
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#define SVSB_MODE_ALL_DISABLE 0
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#define SVSB_MODE_INIT01 BIT(1)
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#define SVSB_MODE_INIT02 BIT(2)
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#define SVSB_MODE_MON BIT(3)
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/* svs bank volt flags */
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#define SVSB_INIT01_PD_REQ BIT(0)
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@ -49,16 +51,21 @@
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#define SVSB_DTLO 0xfe
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#define SVSB_EN_INIT01 0x1
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#define SVSB_EN_INIT02 0x5
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#define SVSB_EN_MON 0x2
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#define SVSB_EN_OFF 0x0
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#define SVSB_INTEN_INIT0x 0x00005f01
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#define SVSB_INTEN_MONVOPEN 0x00ff0000
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#define SVSB_INTSTS_CLEAN 0x00ffffff
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#define SVSB_INTSTS_COMPLETE 0x1
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#define SVSB_INTSTS_MONVOP 0x00ff0000
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#define SVSB_RUNCONFIG_DEFAULT 0x80000000
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/* svs bank related setting */
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#define MAX_OPP_ENTRIES 16
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#define SVSB_DC_SIGNED_BIT BIT(15)
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#define SVSB_DET_CLK_EN BIT(31)
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#define SVSB_TEMP_LOWER_BOUND 0xb2
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#define SVSB_TEMP_UPPER_BOUND 0x64
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static DEFINE_SPINLOCK(svs_lock);
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@ -67,6 +74,7 @@ static DEFINE_SPINLOCK(svs_lock);
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* @SVSB_PHASE_ERROR: svs bank encounters unexpected condition
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* @SVSB_PHASE_INIT01: svs bank basic init for data calibration
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* @SVSB_PHASE_INIT02: svs bank can provide voltages to opp table
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* @SVSB_PHASE_MON: svs bank can provide voltages with thermal effect
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* @SVSB_PHASE_MAX: total number of svs bank phase (debug purpose)
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*
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* Each svs bank has its own independent phase and we enable each svs bank by
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@ -74,12 +82,13 @@ static DEFINE_SPINLOCK(svs_lock);
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* condition, it will fire an irq (PHASE_ERROR) to inform svs software.
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*
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* svs bank general phase-enabled order:
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* SVSB_PHASE_INIT01 -> SVSB_PHASE_INIT02
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* SVSB_PHASE_INIT01 -> SVSB_PHASE_INIT02 -> SVSB_PHASE_MON
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*/
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enum svsb_phase {
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SVSB_PHASE_ERROR = 0,
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SVSB_PHASE_INIT01,
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SVSB_PHASE_INIT02,
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SVSB_PHASE_MON,
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SVSB_PHASE_MAX,
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};
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@ -210,9 +219,11 @@ static const u32 svs_regs_v2[] = {
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* @probe: svs platform probe function pointer
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* @irqflags: svs platform irq settings flags
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* @efuse_max: total number of svs efuse
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* @tefuse_max: total number of thermal efuse
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* @regs: svs platform registers map
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* @bank_max: total number of svs banks
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* @efuse: svs efuse data received from NVMEM framework
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* @tefuse: thermal efuse data received from NVMEM framework
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*/
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struct svs_platform {
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char *name;
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@ -225,9 +236,11 @@ struct svs_platform {
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int (*probe)(struct svs_platform *svsp);
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unsigned long irqflags;
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size_t efuse_max;
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size_t tefuse_max;
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const u32 *regs;
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u32 bank_max;
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u32 *efuse;
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u32 *tefuse;
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};
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struct svs_platform_data {
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@ -246,11 +259,13 @@ struct svs_platform_data {
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* @opp_dev: device for opp table/buck control
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* @init_completion: the timeout completion for bank init
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* @buck: regulator used by opp_dev
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* @tzd: thermal zone device for getting temperature
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* @lock: mutex lock to protect voltage update process
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* @set_freq_pct: function pointer to set bank frequency percent table
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* @get_volts: function pointer to get bank voltages
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* @name: bank name
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* @buck_name: regulator name
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* @tzone_name: thermal zone name
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* @phase: bank current phase
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* @volt_od: bank voltage overdrive
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* @pm_runtime_enabled_count: bank pm runtime enabled count
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@ -279,6 +294,13 @@ struct svs_platform_data {
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* @sw_id: bank software identification
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* @cpu_id: cpu core id for SVS CPU bank use only
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* @ctl0: TS-x selection
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* @temp: bank temperature
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* @tzone_htemp: thermal zone high temperature threshold
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* @tzone_htemp_voffset: thermal zone high temperature voltage offset
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* @tzone_ltemp: thermal zone low temperature threshold
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* @tzone_ltemp_voffset: thermal zone low temperature voltage offset
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* @bts: svs efuse data
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* @mts: svs efuse data
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* @bdes: svs efuse data
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* @mdes: svs efuse data
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* @mtdes: svs efuse data
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@ -295,11 +317,13 @@ struct svs_bank {
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struct device *opp_dev;
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struct completion init_completion;
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struct regulator *buck;
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struct thermal_zone_device *tzd;
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struct mutex lock; /* lock to protect voltage update process */
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void (*set_freq_pct)(struct svs_platform *svsp);
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void (*get_volts)(struct svs_platform *svsp);
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char *name;
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char *buck_name;
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char *tzone_name;
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enum svsb_phase phase;
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s32 volt_od;
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u32 pm_runtime_enabled_count;
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@ -328,6 +352,13 @@ struct svs_bank {
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u32 sw_id;
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u32 cpu_id;
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u32 ctl0;
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u32 temp;
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u32 tzone_htemp;
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u32 tzone_htemp_voffset;
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u32 tzone_ltemp;
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u32 tzone_ltemp_voffset;
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u32 bts;
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u32 mts;
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u32 bdes;
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u32 mdes;
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u32 mtdes;
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@ -370,11 +401,27 @@ static u32 svs_bank_volt_to_opp_volt(u32 svsb_volt, u32 svsb_volt_step,
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static int svs_adjust_pm_opp_volts(struct svs_bank *svsb)
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{
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int ret = -EPERM;
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u32 i, svsb_volt, opp_volt;
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int ret = -EPERM, tzone_temp = 0;
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u32 i, svsb_volt, opp_volt, temp_voffset = 0;
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mutex_lock(&svsb->lock);
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/* Get thermal effect */
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if (svsb->phase == SVSB_PHASE_MON) {
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ret = thermal_zone_get_temp(svsb->tzd, &tzone_temp);
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if (ret || (svsb->temp > SVSB_TEMP_UPPER_BOUND &&
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svsb->temp < SVSB_TEMP_LOWER_BOUND)) {
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dev_err(svsb->dev, "%s: %d (0x%x), run default volts\n",
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svsb->tzone_name, ret, svsb->temp);
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svsb->phase = SVSB_PHASE_ERROR;
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}
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if (tzone_temp >= svsb->tzone_htemp)
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temp_voffset += svsb->tzone_htemp_voffset;
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else if (tzone_temp <= svsb->tzone_ltemp)
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temp_voffset += svsb->tzone_ltemp_voffset;
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}
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/* vmin <= svsb_volt (opp_volt) <= default opp voltage */
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for (i = 0; i < svsb->opp_count; i++) {
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switch (svsb->phase) {
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@ -390,6 +437,12 @@ static int svs_adjust_pm_opp_volts(struct svs_bank *svsb)
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svsb->volt_step,
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svsb->volt_base);
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break;
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case SVSB_PHASE_MON:
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svsb_volt = max(svsb->volt[i] + temp_voffset, svsb->vmin);
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opp_volt = svs_bank_volt_to_opp_volt(svsb_volt,
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svsb->volt_step,
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svsb->volt_base);
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break;
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default:
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dev_err(svsb->dev, "unknown phase: %u\n", svsb->phase);
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ret = -EINVAL;
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@ -484,7 +537,7 @@ static void svs_set_bank_phase(struct svs_platform *svsp,
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enum svsb_phase target_phase)
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{
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struct svs_bank *svsb = svsp->pbank;
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u32 des_char, temp_char, det_char, limit_vals, init2vals;
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u32 des_char, temp_char, det_char, limit_vals, init2vals, ts_calcs;
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svs_switch_bank(svsp);
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@ -525,6 +578,12 @@ static void svs_set_bank_phase(struct svs_platform *svsp,
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svs_writel_relaxed(svsp, init2vals, INIT2VALS);
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svs_writel_relaxed(svsp, SVSB_EN_INIT02, SVSEN);
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break;
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case SVSB_PHASE_MON:
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ts_calcs = (svsb->bts << 12) | svsb->mts;
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svs_writel_relaxed(svsp, ts_calcs, TSCALCS);
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svs_writel_relaxed(svsp, SVSB_INTEN_MONVOPEN, INTEN);
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svs_writel_relaxed(svsp, SVSB_EN_MON, SVSEN);
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break;
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default:
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dev_err(svsb->dev, "requested unknown target phase: %u\n",
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target_phase);
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@ -544,6 +603,7 @@ static inline void svs_error_isr_handler(struct svs_platform *svsp)
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dev_err(svsb->dev, "SMSTATE0 = 0x%08x, SMSTATE1 = 0x%08x\n",
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svs_readl_relaxed(svsp, SMSTATE0),
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svs_readl_relaxed(svsp, SMSTATE1));
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dev_err(svsb->dev, "TEMP = 0x%08x\n", svs_readl_relaxed(svsp, TEMP));
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svsb->phase = SVSB_PHASE_ERROR;
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svs_writel_relaxed(svsp, SVSB_EN_OFF, SVSEN);
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@ -591,6 +651,17 @@ static inline void svs_init02_isr_handler(struct svs_platform *svsp)
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svs_writel_relaxed(svsp, SVSB_INTSTS_COMPLETE, INTSTS);
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}
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static inline void svs_mon_mode_isr_handler(struct svs_platform *svsp)
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{
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struct svs_bank *svsb = svsp->pbank;
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svsb->phase = SVSB_PHASE_MON;
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svsb->get_volts(svsp);
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svsb->temp = svs_readl_relaxed(svsp, TEMP) & GENMASK(7, 0);
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svs_writel_relaxed(svsp, SVSB_INTSTS_MONVOP, INTSTS);
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}
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static irqreturn_t svs_isr(int irq, void *data)
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{
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struct svs_platform *svsp = data;
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@ -621,6 +692,8 @@ static irqreturn_t svs_isr(int irq, void *data)
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else if (int_sts == SVSB_INTSTS_COMPLETE &&
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svs_en == SVSB_EN_INIT02)
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svs_init02_isr_handler(svsp);
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else if (int_sts & SVSB_INTSTS_MONVOP)
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svs_mon_mode_isr_handler(svsp);
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else
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svs_error_isr_handler(svsp);
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@ -835,6 +908,25 @@ static int svs_init02(struct svs_platform *svsp)
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return 0;
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}
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static void svs_mon_mode(struct svs_platform *svsp)
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{
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struct svs_bank *svsb;
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unsigned long flags;
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u32 idx;
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for (idx = 0; idx < svsp->bank_max; idx++) {
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svsb = &svsp->banks[idx];
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if (!(svsb->mode_support & SVSB_MODE_MON))
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continue;
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spin_lock_irqsave(&svs_lock, flags);
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svsp->pbank = svsb;
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svs_set_bank_phase(svsp, SVSB_PHASE_MON);
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spin_unlock_irqrestore(&svs_lock, flags);
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}
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}
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static int svs_start(struct svs_platform *svsp)
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{
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int ret;
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@ -847,6 +939,8 @@ static int svs_start(struct svs_platform *svsp)
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if (ret)
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return ret;
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svs_mon_mode(svsp);
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return 0;
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}
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@ -892,6 +986,8 @@ static int svs_resume(struct device *dev)
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if (ret)
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return ret;
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svs_mon_mode(svsp);
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return 0;
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}
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@ -956,6 +1052,15 @@ static int svs_bank_resource_setup(struct svs_platform *svsp)
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}
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}
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if (svsb->mode_support & SVSB_MODE_MON) {
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svsb->tzd = thermal_zone_get_zone_by_name(svsb->tzone_name);
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if (IS_ERR(svsb->tzd)) {
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dev_err(svsb->dev, "cannot get \"%s\" thermal zone\n",
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svsb->tzone_name);
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return PTR_ERR(svsb->tzd);
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}
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}
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count = dev_pm_opp_get_opp_count(svsb->opp_dev);
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if (svsb->opp_count != count) {
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dev_err(svsb->dev,
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@ -986,7 +1091,11 @@ static int svs_bank_resource_setup(struct svs_platform *svsp)
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static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp)
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{
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struct svs_bank *svsb;
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u32 idx, i, ft_pgm;
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struct nvmem_cell *cell;
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int format[6], x_roomt[6], o_vtsmcu[5], o_vtsabb, tb_roomt = 0;
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int adc_ge_t, adc_oe_t, ge, oe, gain, degc_cali, adc_cali_en_t;
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int o_slope, o_slope_sign, ts_id;
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u32 idx, i, ft_pgm, mts, temp0, temp1, temp2;
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for (i = 0; i < svsp->efuse_max; i++)
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if (svsp->efuse[i])
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@ -1062,6 +1171,127 @@ static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp)
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}
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}
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/* Get thermal efuse by nvmem */
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cell = nvmem_cell_get(svsp->dev, "t-calibration-data");
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if (IS_ERR(cell)) {
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dev_err(svsp->dev, "no \"t-calibration-data\"? %ld\n",
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PTR_ERR(cell));
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goto remove_mt8183_svsb_mon_mode;
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}
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svsp->tefuse = nvmem_cell_read(cell, &svsp->tefuse_max);
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if (IS_ERR(svsp->tefuse)) {
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dev_err(svsp->dev, "cannot read thermal efuse: %ld\n",
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PTR_ERR(svsp->tefuse));
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nvmem_cell_put(cell);
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goto remove_mt8183_svsb_mon_mode;
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}
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svsp->tefuse_max /= sizeof(u32);
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nvmem_cell_put(cell);
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/* Thermal efuse parsing */
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adc_ge_t = (svsp->tefuse[1] >> 22) & GENMASK(9, 0);
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adc_oe_t = (svsp->tefuse[1] >> 12) & GENMASK(9, 0);
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o_vtsmcu[0] = (svsp->tefuse[0] >> 17) & GENMASK(8, 0);
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o_vtsmcu[1] = (svsp->tefuse[0] >> 8) & GENMASK(8, 0);
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o_vtsmcu[2] = svsp->tefuse[1] & GENMASK(8, 0);
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o_vtsmcu[3] = (svsp->tefuse[2] >> 23) & GENMASK(8, 0);
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o_vtsmcu[4] = (svsp->tefuse[2] >> 5) & GENMASK(8, 0);
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o_vtsabb = (svsp->tefuse[2] >> 14) & GENMASK(8, 0);
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degc_cali = (svsp->tefuse[0] >> 1) & GENMASK(5, 0);
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adc_cali_en_t = svsp->tefuse[0] & BIT(0);
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o_slope_sign = (svsp->tefuse[0] >> 7) & BIT(0);
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ts_id = (svsp->tefuse[1] >> 9) & BIT(0);
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o_slope = (svsp->tefuse[0] >> 26) & GENMASK(5, 0);
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if (adc_cali_en_t == 1) {
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if (!ts_id)
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o_slope = 0;
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if (adc_ge_t < 265 || adc_ge_t > 758 ||
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adc_oe_t < 265 || adc_oe_t > 758 ||
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o_vtsmcu[0] < -8 || o_vtsmcu[0] > 484 ||
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o_vtsmcu[1] < -8 || o_vtsmcu[1] > 484 ||
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o_vtsmcu[2] < -8 || o_vtsmcu[2] > 484 ||
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o_vtsmcu[3] < -8 || o_vtsmcu[3] > 484 ||
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o_vtsmcu[4] < -8 || o_vtsmcu[4] > 484 ||
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o_vtsabb < -8 || o_vtsabb > 484 ||
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degc_cali < 1 || degc_cali > 63) {
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dev_err(svsp->dev, "bad thermal efuse, no mon mode\n");
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goto remove_mt8183_svsb_mon_mode;
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}
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} else {
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dev_err(svsp->dev, "no thermal efuse, no mon mode\n");
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goto remove_mt8183_svsb_mon_mode;
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}
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ge = ((adc_ge_t - 512) * 10000) / 4096;
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oe = (adc_oe_t - 512);
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gain = (10000 + ge);
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format[0] = (o_vtsmcu[0] + 3350 - oe);
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format[1] = (o_vtsmcu[1] + 3350 - oe);
|
||||
format[2] = (o_vtsmcu[2] + 3350 - oe);
|
||||
format[3] = (o_vtsmcu[3] + 3350 - oe);
|
||||
format[4] = (o_vtsmcu[4] + 3350 - oe);
|
||||
format[5] = (o_vtsabb + 3350 - oe);
|
||||
|
||||
for (i = 0; i < 6; i++)
|
||||
x_roomt[i] = (((format[i] * 10000) / 4096) * 10000) / gain;
|
||||
|
||||
temp0 = (10000 * 100000 / gain) * 15 / 18;
|
||||
|
||||
if (!o_slope_sign)
|
||||
mts = (temp0 * 10) / (1534 + o_slope * 10);
|
||||
else
|
||||
mts = (temp0 * 10) / (1534 - o_slope * 10);
|
||||
|
||||
for (idx = 0; idx < svsp->bank_max; idx++) {
|
||||
svsb = &svsp->banks[idx];
|
||||
svsb->mts = mts;
|
||||
|
||||
switch (svsb->sw_id) {
|
||||
case SVSB_CPU_LITTLE:
|
||||
tb_roomt = x_roomt[3];
|
||||
break;
|
||||
case SVSB_CPU_BIG:
|
||||
tb_roomt = x_roomt[4];
|
||||
break;
|
||||
case SVSB_CCI:
|
||||
tb_roomt = x_roomt[3];
|
||||
break;
|
||||
case SVSB_GPU:
|
||||
tb_roomt = x_roomt[1];
|
||||
break;
|
||||
default:
|
||||
dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id);
|
||||
goto remove_mt8183_svsb_mon_mode;
|
||||
}
|
||||
|
||||
temp0 = (degc_cali * 10 / 2);
|
||||
temp1 = ((10000 * 100000 / 4096 / gain) *
|
||||
oe + tb_roomt * 10) * 15 / 18;
|
||||
|
||||
if (!o_slope_sign)
|
||||
temp2 = temp1 * 100 / (1534 + o_slope * 10);
|
||||
else
|
||||
temp2 = temp1 * 100 / (1534 - o_slope * 10);
|
||||
|
||||
svsb->bts = (temp0 + temp2 - 250) * 4 / 10;
|
||||
}
|
||||
|
||||
return true;
|
||||
|
||||
remove_mt8183_svsb_mon_mode:
|
||||
for (idx = 0; idx < svsp->bank_max; idx++) {
|
||||
svsb = &svsp->banks[idx];
|
||||
svsb->mode_support &= ~SVSB_MODE_MON;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
@ -1145,9 +1375,15 @@ static struct device *svs_add_device_link(struct svs_platform *svsp,
|
||||
|
||||
static int svs_mt8183_platform_probe(struct svs_platform *svsp)
|
||||
{
|
||||
struct device *dev;
|
||||
struct svs_bank *svsb;
|
||||
u32 idx;
|
||||
|
||||
dev = svs_add_device_link(svsp, "thermal");
|
||||
if (IS_ERR(dev))
|
||||
return dev_err_probe(svsp->dev, PTR_ERR(dev),
|
||||
"failed to get thermal device\n");
|
||||
|
||||
for (idx = 0; idx < svsp->bank_max; idx++) {
|
||||
svsb = &svsp->banks[idx];
|
||||
|
||||
@ -1253,9 +1489,11 @@ static struct svs_bank svs_mt8183_banks[] = {
|
||||
.set_freq_pct = svs_set_bank_freq_pct_v2,
|
||||
.get_volts = svs_get_bank_volts_v2,
|
||||
.buck_name = "mali",
|
||||
.tzone_name = "tzts2",
|
||||
.volt_flags = SVSB_INIT01_PD_REQ |
|
||||
SVSB_INIT01_VOLT_INC_ONLY,
|
||||
.mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02,
|
||||
.mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02 |
|
||||
SVSB_MODE_MON,
|
||||
.opp_count = MAX_OPP_ENTRIES,
|
||||
.freq_base = 900000000,
|
||||
.vboot = 0x30,
|
||||
@ -1271,6 +1509,10 @@ static struct svs_bank svs_mt8183_banks[] = {
|
||||
.core_sel = 0x8fff0003,
|
||||
.int_st = BIT(3),
|
||||
.ctl0 = 0x00050001,
|
||||
.tzone_htemp = 85000,
|
||||
.tzone_htemp_voffset = 0,
|
||||
.tzone_ltemp = 25000,
|
||||
.tzone_ltemp_voffset = 3,
|
||||
},
|
||||
};
|
||||
|
||||
@ -1395,6 +1637,8 @@ svs_probe_clk_disable:
|
||||
svs_probe_free_resource:
|
||||
if (!IS_ERR_OR_NULL(svsp->efuse))
|
||||
kfree(svsp->efuse);
|
||||
if (!IS_ERR_OR_NULL(svsp->tefuse))
|
||||
kfree(svsp->tefuse);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user