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net: ipa: define GSI interrupt types with enums

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Define the GSI global interrupt types with an enumerated type whose
values are the bit positions representing the global interrupt types.

Similarly, define the GSI general interrupt types with an enumerated
type whose values are the bit positions of general interrupt types.

Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Alex Elder 2020-11-10 15:59:17 -06:00 committed by Jakub Kicinski
parent 2f51e5758d
commit 6c6358cca6
2 changed files with 25 additions and 20 deletions
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20
drivers/net/ipa/gsi.c
View File

@ -305,7 +305,7 @@ static void gsi_irq_enable(struct gsi *gsi)
/* Global interrupts include hardware error reports. Enable
* that so we can at least report the error should it occur.
*/
iowrite32(ERROR_INT_FMASK, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET);
iowrite32(BIT(ERROR_INT), gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET);
gsi_irq_type_update(gsi, gsi->type_enabled_bitmap | BIT(GSI_GLOB_EE));
/* General GSI interrupts are reported to all EEs; if they occur
@ -313,9 +313,9 @@ static void gsi_irq_enable(struct gsi *gsi)
* also exists, but we don't support that. We want to be notified
* of errors so we can report them, even if they can't be handled.
*/
val = BUS_ERROR_FMASK;
val |= CMD_FIFO_OVRFLOW_FMASK;
val |= MCS_STACK_OVRFLOW_FMASK;
val = BIT(BUS_ERROR);
val |= BIT(CMD_FIFO_OVRFLOW);
val |= BIT(MCS_STACK_OVRFLOW);
iowrite32(val, gsi->virt + GSI_CNTXT_GSI_IRQ_EN_OFFSET);
gsi_irq_type_update(gsi, gsi->type_enabled_bitmap | BIT(GSI_GENERAL));
}
@ -1145,15 +1145,15 @@ static void gsi_isr_glob_ee(struct gsi *gsi)
val = ioread32(gsi->virt + GSI_CNTXT_GLOB_IRQ_STTS_OFFSET);
if (val & ERROR_INT_FMASK)
if (val & BIT(ERROR_INT))
gsi_isr_glob_err(gsi);
iowrite32(val, gsi->virt + GSI_CNTXT_GLOB_IRQ_CLR_OFFSET);
val &= ~ERROR_INT_FMASK;
val &= ~BIT(ERROR_INT);
if (val & GP_INT1_FMASK) {
val ^= GP_INT1_FMASK;
if (val & BIT(GP_INT1)) {
val ^= BIT(GP_INT1);
gsi_isr_gp_int1(gsi);
}
@ -1626,7 +1626,7 @@ static int gsi_generic_command(struct gsi *gsi, u32 channel_id,
* halt a modem channel) and only from this function. So we
* enable the GP_INT1 IRQ type here while we're expecting it.
*/
val = ERROR_INT_FMASK | GP_INT1_FMASK;
val = BIT(ERROR_INT) | BIT(GP_INT1);
iowrite32(val, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET);
/* First zero the result code field */
@ -1642,7 +1642,7 @@ static int gsi_generic_command(struct gsi *gsi, u32 channel_id,
success = gsi_command(gsi, GSI_GENERIC_CMD_OFFSET, val, completion);
/* Disable the GP_INT1 IRQ type again */
iowrite32(ERROR_INT_FMASK, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET);
iowrite32(BIT(ERROR_INT), gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET);
if (success)
return 0;

25
drivers/net/ipa/gsi_reg.h
View File

@ -254,6 +254,7 @@
#define GSI_USE_RD_WR_ENG_FMASK GENMASK(30, 30)
#define GSI_USE_INTER_EE_FMASK GENMASK(31, 31)
/* IRQ condition for each type is cleared by writing type-specific register */
#define GSI_CNTXT_TYPE_IRQ_OFFSET \
GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(GSI_EE_AP)
#define GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(ee) \
@ -330,11 +331,13 @@ enum gsi_irq_type_id {
GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(GSI_EE_AP)
#define GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(ee) \
(0x0001f110 + 0x4000 * (ee))
/* The masks below are used for the general IRQ STTS, EN, and CLR registers */
#define ERROR_INT_FMASK GENMASK(0, 0)
#define GP_INT1_FMASK GENMASK(1, 1)
#define GP_INT2_FMASK GENMASK(2, 2)
#define GP_INT3_FMASK GENMASK(3, 3)
/* Values here are bit positions in the GLOB_IRQ_* registers */
enum gsi_global_irq_id {
ERROR_INT = 0x0,
GP_INT1 = 0x1,
GP_INT2 = 0x2,
GP_INT3 = 0x3,
};
#define GSI_CNTXT_GSI_IRQ_STTS_OFFSET \
GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(GSI_EE_AP)
@ -348,11 +351,13 @@ enum gsi_irq_type_id {
GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(GSI_EE_AP)
#define GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(ee) \
(0x0001f128 + 0x4000 * (ee))
/* The masks below are used for the general IRQ STTS, EN, and CLR registers */
#define BREAK_POINT_FMASK GENMASK(0, 0)
#define BUS_ERROR_FMASK GENMASK(1, 1)
#define CMD_FIFO_OVRFLOW_FMASK GENMASK(2, 2)
#define MCS_STACK_OVRFLOW_FMASK GENMASK(3, 3)
/* Values here are bit positions in the (general) GSI_IRQ_* registers */
enum gsi_general_id {
BREAK_POINT = 0x0,
BUS_ERROR = 0x1,
CMD_FIFO_OVRFLOW = 0x2,
MCS_STACK_OVRFLOW = 0x3,
};
#define GSI_CNTXT_INTSET_OFFSET \
GSI_EE_N_CNTXT_INTSET_OFFSET(GSI_EE_AP)