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dmaengine: milbeaut-hdmac: Add HDMAC driver for Milbeaut platforms
Driver for Socionext Milbeaut HDMAC controller. The controller has upto 8 floating channels, that need a predefined slave-id to work from a set of slaves. Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> Link: https://lore.kernel.org/r/20191015033359.14925-1-jassisinghbrar@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Jassi Brar
Vinod Koul
parent
df781c0cee
commit
6c3214e698
@ -342,6 +342,16 @@ config MCF_EDMA
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minimal intervention from a host processor.
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This module can be found on Freescale ColdFire mcf5441x SoCs.
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config MILBEAUT_HDMAC
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tristate "Milbeaut AHB DMA support"
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depends on ARCH_MILBEAUT || COMPILE_TEST
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depends on OF
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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help
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Say yes here to support the Socionext Milbeaut
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HDMAC device.
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config MMP_PDMA
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bool "MMP PDMA support"
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depends on ARCH_MMP || ARCH_PXA || COMPILE_TEST
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@ -45,6 +45,7 @@ obj-$(CONFIG_INTEL_IOP_ADMA) += iop-adma.o
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obj-$(CONFIG_INTEL_MIC_X100_DMA) += mic_x100_dma.o
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obj-$(CONFIG_K3_DMA) += k3dma.o
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obj-$(CONFIG_LPC18XX_DMAMUX) += lpc18xx-dmamux.o
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obj-$(CONFIG_MILBEAUT_HDMAC) += milbeaut-hdmac.o
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obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o
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obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o
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obj-$(CONFIG_MOXART_DMA) += moxart-dma.o
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581
drivers/dma/milbeaut-hdmac.c
Normal file
581
drivers/dma/milbeaut-hdmac.c
Normal file
@ -0,0 +1,581 @@
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// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright (C) 2019 Linaro Ltd.
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// Copyright (C) 2019 Socionext Inc.
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#include <linux/bits.h>
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#include <linux/clk.h>
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#include <linux/dma-mapping.h>
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#include <linux/interrupt.h>
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#include <linux/iopoll.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/of_dma.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#include <linux/bitfield.h>
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#include "virt-dma.h"
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#define MLB_HDMAC_DMACR 0x0 /* global */
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#define MLB_HDMAC_DE BIT(31)
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#define MLB_HDMAC_DS BIT(30)
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#define MLB_HDMAC_PR BIT(28)
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#define MLB_HDMAC_DH GENMASK(27, 24)
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#define MLB_HDMAC_CH_STRIDE 0x10
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#define MLB_HDMAC_DMACA 0x0 /* channel */
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#define MLB_HDMAC_EB BIT(31)
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#define MLB_HDMAC_PB BIT(30)
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#define MLB_HDMAC_ST BIT(29)
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#define MLB_HDMAC_IS GENMASK(28, 24)
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#define MLB_HDMAC_BT GENMASK(23, 20)
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#define MLB_HDMAC_BC GENMASK(19, 16)
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#define MLB_HDMAC_TC GENMASK(15, 0)
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#define MLB_HDMAC_DMACB 0x4
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#define MLB_HDMAC_TT GENMASK(31, 30)
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#define MLB_HDMAC_MS GENMASK(29, 28)
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#define MLB_HDMAC_TW GENMASK(27, 26)
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#define MLB_HDMAC_FS BIT(25)
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#define MLB_HDMAC_FD BIT(24)
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#define MLB_HDMAC_RC BIT(23)
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#define MLB_HDMAC_RS BIT(22)
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#define MLB_HDMAC_RD BIT(21)
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#define MLB_HDMAC_EI BIT(20)
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#define MLB_HDMAC_CI BIT(19)
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#define HDMAC_PAUSE 0x7
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#define MLB_HDMAC_SS GENMASK(18, 16)
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#define MLB_HDMAC_SP GENMASK(15, 12)
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#define MLB_HDMAC_DP GENMASK(11, 8)
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#define MLB_HDMAC_DMACSA 0x8
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#define MLB_HDMAC_DMACDA 0xc
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#define MLB_HDMAC_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
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BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
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BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
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struct milbeaut_hdmac_desc {
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struct virt_dma_desc vd;
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struct scatterlist *sgl;
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unsigned int sg_len;
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unsigned int sg_cur;
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enum dma_transfer_direction dir;
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};
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struct milbeaut_hdmac_chan {
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struct virt_dma_chan vc;
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struct milbeaut_hdmac_device *mdev;
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struct milbeaut_hdmac_desc *md;
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void __iomem *reg_ch_base;
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unsigned int slave_id;
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struct dma_slave_config cfg;
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};
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struct milbeaut_hdmac_device {
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struct dma_device ddev;
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struct clk *clk;
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void __iomem *reg_base;
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struct milbeaut_hdmac_chan channels[0];
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};
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static struct milbeaut_hdmac_chan *
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to_milbeaut_hdmac_chan(struct virt_dma_chan *vc)
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{
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return container_of(vc, struct milbeaut_hdmac_chan, vc);
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}
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static struct milbeaut_hdmac_desc *
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to_milbeaut_hdmac_desc(struct virt_dma_desc *vd)
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{
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return container_of(vd, struct milbeaut_hdmac_desc, vd);
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}
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/* mc->vc.lock must be held by caller */
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static struct milbeaut_hdmac_desc *
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milbeaut_hdmac_next_desc(struct milbeaut_hdmac_chan *mc)
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{
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struct virt_dma_desc *vd;
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vd = vchan_next_desc(&mc->vc);
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if (!vd) {
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mc->md = NULL;
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return NULL;
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}
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list_del(&vd->node);
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mc->md = to_milbeaut_hdmac_desc(vd);
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return mc->md;
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}
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/* mc->vc.lock must be held by caller */
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static void milbeaut_chan_start(struct milbeaut_hdmac_chan *mc,
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struct milbeaut_hdmac_desc *md)
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{
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struct scatterlist *sg;
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u32 cb, ca, src_addr, dest_addr, len;
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u32 width, burst;
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sg = &md->sgl[md->sg_cur];
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len = sg_dma_len(sg);
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cb = MLB_HDMAC_CI | MLB_HDMAC_EI;
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if (md->dir == DMA_MEM_TO_DEV) {
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cb |= MLB_HDMAC_FD;
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width = mc->cfg.dst_addr_width;
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burst = mc->cfg.dst_maxburst;
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src_addr = sg_dma_address(sg);
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dest_addr = mc->cfg.dst_addr;
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} else {
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cb |= MLB_HDMAC_FS;
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width = mc->cfg.src_addr_width;
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burst = mc->cfg.src_maxburst;
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src_addr = mc->cfg.src_addr;
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dest_addr = sg_dma_address(sg);
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}
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cb |= FIELD_PREP(MLB_HDMAC_TW, (width >> 1));
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cb |= FIELD_PREP(MLB_HDMAC_MS, 2);
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writel_relaxed(MLB_HDMAC_DE, mc->mdev->reg_base + MLB_HDMAC_DMACR);
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writel_relaxed(src_addr, mc->reg_ch_base + MLB_HDMAC_DMACSA);
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writel_relaxed(dest_addr, mc->reg_ch_base + MLB_HDMAC_DMACDA);
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writel_relaxed(cb, mc->reg_ch_base + MLB_HDMAC_DMACB);
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ca = FIELD_PREP(MLB_HDMAC_IS, mc->slave_id);
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if (burst == 16)
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ca |= FIELD_PREP(MLB_HDMAC_BT, 0xf);
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else if (burst == 8)
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ca |= FIELD_PREP(MLB_HDMAC_BT, 0xd);
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else if (burst == 4)
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ca |= FIELD_PREP(MLB_HDMAC_BT, 0xb);
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burst *= width;
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ca |= FIELD_PREP(MLB_HDMAC_TC, (len / burst - 1));
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writel_relaxed(ca, mc->reg_ch_base + MLB_HDMAC_DMACA);
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ca |= MLB_HDMAC_EB;
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writel_relaxed(ca, mc->reg_ch_base + MLB_HDMAC_DMACA);
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}
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/* mc->vc.lock must be held by caller */
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static void milbeaut_hdmac_start(struct milbeaut_hdmac_chan *mc)
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{
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struct milbeaut_hdmac_desc *md;
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md = milbeaut_hdmac_next_desc(mc);
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if (md)
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milbeaut_chan_start(mc, md);
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}
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static irqreturn_t milbeaut_hdmac_interrupt(int irq, void *dev_id)
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{
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struct milbeaut_hdmac_chan *mc = dev_id;
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struct milbeaut_hdmac_desc *md;
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u32 val;
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spin_lock(&mc->vc.lock);
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/* Ack and Disable irqs */
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val = readl_relaxed(mc->reg_ch_base + MLB_HDMAC_DMACB);
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val &= ~(FIELD_PREP(MLB_HDMAC_SS, HDMAC_PAUSE));
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writel_relaxed(val, mc->reg_ch_base + MLB_HDMAC_DMACB);
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val &= ~MLB_HDMAC_EI;
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val &= ~MLB_HDMAC_CI;
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writel_relaxed(val, mc->reg_ch_base + MLB_HDMAC_DMACB);
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md = mc->md;
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if (!md)
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goto out;
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md->sg_cur++;
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if (md->sg_cur >= md->sg_len) {
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vchan_cookie_complete(&md->vd);
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md = milbeaut_hdmac_next_desc(mc);
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if (!md)
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goto out;
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}
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milbeaut_chan_start(mc, md);
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out:
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spin_unlock(&mc->vc.lock);
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return IRQ_HANDLED;
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}
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static void milbeaut_hdmac_free_chan_resources(struct dma_chan *chan)
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{
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vchan_free_chan_resources(to_virt_chan(chan));
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}
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static int
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milbeaut_hdmac_chan_config(struct dma_chan *chan, struct dma_slave_config *cfg)
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{
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struct virt_dma_chan *vc = to_virt_chan(chan);
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struct milbeaut_hdmac_chan *mc = to_milbeaut_hdmac_chan(vc);
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spin_lock(&mc->vc.lock);
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mc->cfg = *cfg;
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spin_unlock(&mc->vc.lock);
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return 0;
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}
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static int milbeaut_hdmac_chan_pause(struct dma_chan *chan)
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{
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struct virt_dma_chan *vc = to_virt_chan(chan);
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struct milbeaut_hdmac_chan *mc = to_milbeaut_hdmac_chan(vc);
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u32 val;
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spin_lock(&mc->vc.lock);
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val = readl_relaxed(mc->reg_ch_base + MLB_HDMAC_DMACA);
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val |= MLB_HDMAC_PB;
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writel_relaxed(val, mc->reg_ch_base + MLB_HDMAC_DMACA);
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spin_unlock(&mc->vc.lock);
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return 0;
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}
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static int milbeaut_hdmac_chan_resume(struct dma_chan *chan)
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{
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struct virt_dma_chan *vc = to_virt_chan(chan);
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struct milbeaut_hdmac_chan *mc = to_milbeaut_hdmac_chan(vc);
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u32 val;
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spin_lock(&mc->vc.lock);
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val = readl_relaxed(mc->reg_ch_base + MLB_HDMAC_DMACA);
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val &= ~MLB_HDMAC_PB;
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writel_relaxed(val, mc->reg_ch_base + MLB_HDMAC_DMACA);
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spin_unlock(&mc->vc.lock);
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return 0;
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}
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static struct dma_async_tx_descriptor *
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milbeaut_hdmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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unsigned int sg_len,
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enum dma_transfer_direction direction,
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unsigned long flags, void *context)
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{
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struct virt_dma_chan *vc = to_virt_chan(chan);
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struct milbeaut_hdmac_desc *md;
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int i;
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if (!is_slave_direction(direction))
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return NULL;
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md = kzalloc(sizeof(*md), GFP_NOWAIT);
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if (!md)
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return NULL;
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md->sgl = kzalloc(sizeof(*sgl) * sg_len, GFP_NOWAIT);
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if (!md->sgl) {
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kfree(md);
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return NULL;
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}
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for (i = 0; i < sg_len; i++)
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md->sgl[i] = sgl[i];
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md->sg_len = sg_len;
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md->dir = direction;
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return vchan_tx_prep(vc, &md->vd, flags);
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}
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static int milbeaut_hdmac_terminate_all(struct dma_chan *chan)
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{
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struct virt_dma_chan *vc = to_virt_chan(chan);
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struct milbeaut_hdmac_chan *mc = to_milbeaut_hdmac_chan(vc);
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unsigned long flags;
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u32 val;
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LIST_HEAD(head);
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spin_lock_irqsave(&vc->lock, flags);
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val = readl_relaxed(mc->reg_ch_base + MLB_HDMAC_DMACA);
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val &= ~MLB_HDMAC_EB; /* disable the channel */
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writel_relaxed(val, mc->reg_ch_base + MLB_HDMAC_DMACA);
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if (mc->md) {
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vchan_terminate_vdesc(&mc->md->vd);
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mc->md = NULL;
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}
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vchan_get_all_descriptors(vc, &head);
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spin_unlock_irqrestore(&vc->lock, flags);
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vchan_dma_desc_free_list(vc, &head);
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return 0;
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}
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static void milbeaut_hdmac_synchronize(struct dma_chan *chan)
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{
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vchan_synchronize(to_virt_chan(chan));
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}
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static enum dma_status milbeaut_hdmac_tx_status(struct dma_chan *chan,
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dma_cookie_t cookie,
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struct dma_tx_state *txstate)
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{
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struct virt_dma_chan *vc;
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struct virt_dma_desc *vd;
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struct milbeaut_hdmac_chan *mc;
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struct milbeaut_hdmac_desc *md = NULL;
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enum dma_status stat;
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unsigned long flags;
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int i;
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stat = dma_cookie_status(chan, cookie, txstate);
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/* Return immediately if we do not need to compute the residue. */
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if (stat == DMA_COMPLETE || !txstate)
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return stat;
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vc = to_virt_chan(chan);
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spin_lock_irqsave(&vc->lock, flags);
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mc = to_milbeaut_hdmac_chan(vc);
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/* residue from the on-flight chunk */
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if (mc->md && mc->md->vd.tx.cookie == cookie) {
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struct scatterlist *sg;
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u32 done;
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md = mc->md;
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sg = &md->sgl[md->sg_cur];
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if (md->dir == DMA_DEV_TO_MEM)
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done = readl_relaxed(mc->reg_ch_base
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+ MLB_HDMAC_DMACDA);
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else
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done = readl_relaxed(mc->reg_ch_base
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+ MLB_HDMAC_DMACSA);
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done -= sg_dma_address(sg);
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txstate->residue = -done;
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}
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if (!md) {
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vd = vchan_find_desc(vc, cookie);
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if (vd)
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md = to_milbeaut_hdmac_desc(vd);
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}
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if (md) {
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/* residue from the queued chunks */
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for (i = md->sg_cur; i < md->sg_len; i++)
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txstate->residue += sg_dma_len(&md->sgl[i]);
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}
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spin_unlock_irqrestore(&vc->lock, flags);
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return stat;
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}
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static void milbeaut_hdmac_issue_pending(struct dma_chan *chan)
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{
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struct virt_dma_chan *vc = to_virt_chan(chan);
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struct milbeaut_hdmac_chan *mc = to_milbeaut_hdmac_chan(vc);
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unsigned long flags;
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spin_lock_irqsave(&vc->lock, flags);
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if (vchan_issue_pending(vc) && !mc->md)
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milbeaut_hdmac_start(mc);
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spin_unlock_irqrestore(&vc->lock, flags);
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}
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static void milbeaut_hdmac_desc_free(struct virt_dma_desc *vd)
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{
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struct milbeaut_hdmac_desc *md = to_milbeaut_hdmac_desc(vd);
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kfree(md->sgl);
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kfree(md);
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}
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static struct dma_chan *
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milbeaut_hdmac_xlate(struct of_phandle_args *dma_spec, struct of_dma *of_dma)
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{
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struct milbeaut_hdmac_device *mdev = of_dma->of_dma_data;
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struct milbeaut_hdmac_chan *mc;
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struct virt_dma_chan *vc;
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struct dma_chan *chan;
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if (dma_spec->args_count != 1)
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return NULL;
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chan = dma_get_any_slave_channel(&mdev->ddev);
|
||||
if (!chan)
|
||||
return NULL;
|
||||
|
||||
vc = to_virt_chan(chan);
|
||||
mc = to_milbeaut_hdmac_chan(vc);
|
||||
mc->slave_id = dma_spec->args[0];
|
||||
|
||||
return chan;
|
||||
}
|
||||
|
||||
static int milbeaut_hdmac_chan_init(struct platform_device *pdev,
|
||||
struct milbeaut_hdmac_device *mdev,
|
||||
int chan_id)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct milbeaut_hdmac_chan *mc = &mdev->channels[chan_id];
|
||||
char *irq_name;
|
||||
int irq, ret;
|
||||
|
||||
irq = platform_get_irq(pdev, chan_id);
|
||||
if (irq < 0) {
|
||||
dev_err(&pdev->dev, "failed to get IRQ number for ch%d\n",
|
||||
chan_id);
|
||||
return irq;
|
||||
}
|
||||
|
||||
irq_name = devm_kasprintf(dev, GFP_KERNEL, "milbeaut-hdmac-%d",
|
||||
chan_id);
|
||||
if (!irq_name)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = devm_request_irq(dev, irq, milbeaut_hdmac_interrupt,
|
||||
IRQF_SHARED, irq_name, mc);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
mc->mdev = mdev;
|
||||
mc->reg_ch_base = mdev->reg_base + MLB_HDMAC_CH_STRIDE * (chan_id + 1);
|
||||
mc->vc.desc_free = milbeaut_hdmac_desc_free;
|
||||
vchan_init(&mc->vc, &mdev->ddev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int milbeaut_hdmac_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct milbeaut_hdmac_device *mdev;
|
||||
struct dma_device *ddev;
|
||||
int nr_chans, ret, i;
|
||||
|
||||
nr_chans = platform_irq_count(pdev);
|
||||
if (nr_chans < 0)
|
||||
return nr_chans;
|
||||
|
||||
ret = dma_set_mask(dev, DMA_BIT_MASK(32));
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
mdev = devm_kzalloc(dev, struct_size(mdev, channels, nr_chans),
|
||||
GFP_KERNEL);
|
||||
if (!mdev)
|
||||
return -ENOMEM;
|
||||
|
||||
mdev->reg_base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(mdev->reg_base))
|
||||
return PTR_ERR(mdev->reg_base);
|
||||
|
||||
mdev->clk = devm_clk_get(dev, NULL);
|
||||
if (IS_ERR(mdev->clk)) {
|
||||
dev_err(dev, "failed to get clock\n");
|
||||
return PTR_ERR(mdev->clk);
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(mdev->clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ddev = &mdev->ddev;
|
||||
ddev->dev = dev;
|
||||
dma_cap_set(DMA_SLAVE, ddev->cap_mask);
|
||||
dma_cap_set(DMA_PRIVATE, ddev->cap_mask);
|
||||
ddev->src_addr_widths = MLB_HDMAC_BUSWIDTHS;
|
||||
ddev->dst_addr_widths = MLB_HDMAC_BUSWIDTHS;
|
||||
ddev->directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);
|
||||
ddev->device_free_chan_resources = milbeaut_hdmac_free_chan_resources;
|
||||
ddev->device_config = milbeaut_hdmac_chan_config;
|
||||
ddev->device_pause = milbeaut_hdmac_chan_pause;
|
||||
ddev->device_resume = milbeaut_hdmac_chan_resume;
|
||||
ddev->device_prep_slave_sg = milbeaut_hdmac_prep_slave_sg;
|
||||
ddev->device_terminate_all = milbeaut_hdmac_terminate_all;
|
||||
ddev->device_synchronize = milbeaut_hdmac_synchronize;
|
||||
ddev->device_tx_status = milbeaut_hdmac_tx_status;
|
||||
ddev->device_issue_pending = milbeaut_hdmac_issue_pending;
|
||||
INIT_LIST_HEAD(&ddev->channels);
|
||||
|
||||
for (i = 0; i < nr_chans; i++) {
|
||||
ret = milbeaut_hdmac_chan_init(pdev, mdev, i);
|
||||
if (ret)
|
||||
goto disable_clk;
|
||||
}
|
||||
|
||||
ret = dma_async_device_register(ddev);
|
||||
if (ret)
|
||||
goto disable_clk;
|
||||
|
||||
ret = of_dma_controller_register(dev->of_node,
|
||||
milbeaut_hdmac_xlate, mdev);
|
||||
if (ret)
|
||||
goto unregister_dmac;
|
||||
|
||||
platform_set_drvdata(pdev, mdev);
|
||||
|
||||
return 0;
|
||||
|
||||
unregister_dmac:
|
||||
dma_async_device_unregister(ddev);
|
||||
disable_clk:
|
||||
clk_disable_unprepare(mdev->clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int milbeaut_hdmac_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct milbeaut_hdmac_device *mdev = platform_get_drvdata(pdev);
|
||||
struct dma_chan *chan;
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* Before reaching here, almost all descriptors have been freed by the
|
||||
* ->device_free_chan_resources() hook. However, each channel might
|
||||
* be still holding one descriptor that was on-flight at that moment.
|
||||
* Terminate it to make sure this hardware is no longer running. Then,
|
||||
* free the channel resources once again to avoid memory leak.
|
||||
*/
|
||||
list_for_each_entry(chan, &mdev->ddev.channels, device_node) {
|
||||
ret = dmaengine_terminate_sync(chan);
|
||||
if (ret)
|
||||
return ret;
|
||||
milbeaut_hdmac_free_chan_resources(chan);
|
||||
}
|
||||
|
||||
of_dma_controller_free(pdev->dev.of_node);
|
||||
dma_async_device_unregister(&mdev->ddev);
|
||||
clk_disable_unprepare(mdev->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id milbeaut_hdmac_match[] = {
|
||||
{ .compatible = "socionext,milbeaut-m10v-hdmac" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, milbeaut_hdmac_match);
|
||||
|
||||
static struct platform_driver milbeaut_hdmac_driver = {
|
||||
.probe = milbeaut_hdmac_probe,
|
||||
.remove = milbeaut_hdmac_remove,
|
||||
.driver = {
|
||||
.name = "milbeaut-m10v-hdmac",
|
||||
.of_match_table = milbeaut_hdmac_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(milbeaut_hdmac_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Milbeaut HDMAC DmaEngine driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in New Issue
Block a user