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ARM: rockchip: add support for rk3188 and Radxa Rock board
Basic devicetree files for the rk3188 SoC. Also provided is a board dts file for the upcoming Radxa Rock board using this SoC. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Heiko Stuebner
parent
9586609619
commit
6bcf60f8d5
289
arch/arm/boot/dts/rk3188-clocks.dtsi
Normal file
289
arch/arm/boot/dts/rk3188-clocks.dtsi
Normal file
@ -0,0 +1,289 @@
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/*
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* Copyright (c) 2013 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/ {
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/*
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* This is a dummy clock, to be used as placeholder on
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* other mux clocks when a specific parent clock is not
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* yet implemented. It should be dropped when the driver
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* is complete.
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*/
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dummy: dummy {
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compatible = "fixed-clock";
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clock-frequency = <0>;
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#clock-cells = <0>;
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};
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xin24m: xin24m {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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#clock-cells = <0>;
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};
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dummy48m: dummy48m {
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compatible = "fixed-clock";
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clock-frequency = <48000000>;
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#clock-cells = <0>;
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};
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dummy150m: dummy150m {
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compatible = "fixed-clock";
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clock-frequency = <150000000>;
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#clock-cells = <0>;
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};
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clk_gates0: gate-clk@200000d0 {
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compatible = "rockchip,rk2928-gate-clk";
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reg = <0x200000d0 0x4>;
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clocks = <&dummy150m>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>;
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clock-output-names =
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"gate_core_periph", "gate_cpu_gpll",
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"gate_ddrphy", "gate_aclk_cpu",
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"gate_hclk_cpu", "gate_pclk_cpu",
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"gate_atclk_cpu", "gate_aclk_core",
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"reserved", "gate_i2s0",
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"gate_i2s0_frac", "reserved",
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"reserved", "gate_spdif",
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"gate_spdif_frac", "gate_testclk";
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#clock-cells = <1>;
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};
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clk_gates1: gate-clk@200000d4 {
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compatible = "rockchip,rk2928-gate-clk";
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reg = <0x200000d4 0x4>;
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clocks = <&xin24m>, <&xin24m>,
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<&xin24m>, <&dummy>,
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<&dummy>, <&xin24m>,
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<&xin24m>, <&dummy>,
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<&xin24m>, <&dummy>,
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<&xin24m>, <&dummy>,
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<&xin24m>, <&dummy>,
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<&xin24m>, <&dummy>;
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clock-output-names =
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"gate_timer0", "gate_timer1",
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"gate_timer3", "gate_jtag",
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"gate_aclk_lcdc1_src", "gate_otgphy0",
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"gate_otgphy1", "gate_ddr_gpll",
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"gate_uart0", "gate_frac_uart0",
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"gate_uart1", "gate_frac_uart1",
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"gate_uart2", "gate_frac_uart2",
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"gate_uart3", "gate_frac_uart3";
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#clock-cells = <1>;
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};
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clk_gates2: gate-clk@200000d8 {
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compatible = "rockchip,rk2928-gate-clk";
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reg = <0x200000d8 0x4>;
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clocks = <&clk_gates2 1>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&clk_gates2 3>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy48m>,
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<&dummy>, <&dummy48m>,
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<&dummy>, <&dummy>;
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clock-output-names =
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"gate_periph_src", "gate_aclk_periph",
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"gate_hclk_periph", "gate_pclk_periph",
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"gate_smc", "gate_mac",
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"gate_hsadc", "gate_hsadc_frac",
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"gate_saradc", "gate_spi0",
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"gate_spi1", "gate_mmc0",
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"gate_mac_lbtest", "gate_mmc1",
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"gate_emmc", "reserved";
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#clock-cells = <1>;
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};
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clk_gates3: gate-clk@200000dc {
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compatible = "rockchip,rk2928-gate-clk";
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reg = <0x200000dc 0x4>;
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clocks = <&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&xin24m>, <&xin24m>,
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<&dummy>, <&dummy>,
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<&xin24m>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&xin24m>, <&dummy>;
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clock-output-names =
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"gate_aclk_lcdc0_src", "gate_dclk_lcdc0",
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"gate_dclk_lcdc1", "gate_pclkin_cif0",
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"gate_timer2", "gate_timer4",
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"gate_hsicphy", "gate_cif0_out",
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"gate_timer5", "gate_aclk_vepu",
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"gate_hclk_vepu", "gate_aclk_vdpu",
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"gate_hclk_vdpu", "reserved",
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"gate_timer6", "gate_aclk_gpu_src";
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#clock-cells = <1>;
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};
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clk_gates4: gate-clk@200000e0 {
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compatible = "rockchip,rk2928-gate-clk";
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reg = <0x200000e0 0x4>;
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clocks = <&clk_gates2 2>, <&clk_gates2 3>,
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<&clk_gates2 1>, <&clk_gates2 1>,
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<&clk_gates2 1>, <&clk_gates2 2>,
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<&clk_gates2 2>, <&clk_gates2 2>,
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<&clk_gates0 4>, <&clk_gates0 4>,
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<&clk_gates0 3>, <&dummy>,
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<&clk_gates0 3>, <&dummy>,
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<&dummy>, <&dummy>;
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clock-output-names =
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"gate_hclk_peri_axi_matrix", "gate_pclk_peri_axi_matrix",
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"gate_aclk_cpu_peri", "gate_aclk_peri_axi_matrix",
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"gate_aclk_pei_niu", "gate_hclk_usb_peri",
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"gate_hclk_peri_ahb_arbi", "gate_hclk_emem_peri",
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"gate_hclk_cpubus", "gate_hclk_ahb2apb",
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"gate_aclk_strc_sys", "reserved",
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"gate_aclk_intmem", "reserved",
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"gate_hclk_imem1", "gate_hclk_imem0";
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#clock-cells = <1>;
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};
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clk_gates5: gate-clk@200000e4 {
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compatible = "rockchip,rk2928-gate-clk";
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reg = <0x200000e4 0x4>;
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clocks = <&clk_gates0 3>, <&clk_gates2 1>,
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<&clk_gates0 5>, <&clk_gates0 5>,
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<&clk_gates0 5>, <&clk_gates0 5>,
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<&clk_gates0 4>, <&clk_gates0 5>,
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<&clk_gates2 1>, <&clk_gates2 2>,
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<&clk_gates2 2>, <&clk_gates2 2>,
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<&clk_gates2 2>, <&clk_gates4 5>;
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clock-output-names =
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"gate_aclk_dmac1", "gate_aclk_dmac2",
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"gate_pclk_efuse", "gate_pclk_tzpc",
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"gate_pclk_grf", "gate_pclk_pmu",
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"gate_hclk_rom", "gate_pclk_ddrupctl",
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"gate_aclk_smc", "gate_hclk_nandc",
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"gate_hclk_mmc0", "gate_hclk_mmc1",
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"gate_hclk_emmc", "gate_hclk_otg0";
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#clock-cells = <1>;
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};
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clk_gates6: gate-clk@200000e8 {
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compatible = "rockchip,rk2928-gate-clk";
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reg = <0x200000e8 0x4>;
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clocks = <&clk_gates3 0>, <&clk_gates0 4>,
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<&clk_gates0 4>, <&clk_gates1 4>,
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<&clk_gates0 4>, <&clk_gates3 0>,
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<&dummy>, <&dummy>,
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<&clk_gates3 0>, <&clk_gates0 4>,
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<&clk_gates0 4>, <&clk_gates1 4>,
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<&clk_gates0 4>, <&clk_gates3 0>;
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clock-output-names =
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"gate_aclk_lcdc0", "gate_hclk_lcdc0",
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"gate_hclk_lcdc1", "gate_aclk_lcdc1",
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"gate_hclk_cif0", "gate_aclk_cif0",
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"reserved", "reserved",
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"gate_aclk_ipp", "gate_hclk_ipp",
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"gate_hclk_rga", "gate_aclk_rga",
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"gate_hclk_vio_bus", "gate_aclk_vio0";
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#clock-cells = <1>;
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};
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clk_gates7: gate-clk@200000ec {
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compatible = "rockchip,rk2928-gate-clk";
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reg = <0x200000ec 0x4>;
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clocks = <&clk_gates2 2>, <&clk_gates0 4>,
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<&clk_gates0 4>, <&dummy>,
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<&dummy>, <&clk_gates2 2>,
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<&clk_gates2 2>, <&clk_gates0 5>,
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<&dummy>, <&clk_gates0 5>,
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<&clk_gates0 5>, <&clk_gates2 3>,
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<&clk_gates2 3>, <&clk_gates2 3>,
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<&clk_gates2 3>, <&clk_gates2 3>;
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clock-output-names =
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"gate_hclk_emac", "gate_hclk_spdif",
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"gate_hclk_i2s0_2ch", "gate_hclk_otg1",
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"gate_hclk_hsic", "gate_hclk_hsadc",
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"gate_hclk_pidf", "gate_pclk_timer0",
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"reserved", "gate_pclk_timer2",
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"gate_pclk_pwm01", "gate_pclk_pwm23",
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"gate_pclk_spi0", "gate_pclk_spi1",
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"gate_pclk_saradc", "gate_pclk_wdt";
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#clock-cells = <1>;
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};
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clk_gates8: gate-clk@200000f0 {
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compatible = "rockchip,rk2928-gate-clk";
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reg = <0x200000f0 0x4>;
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clocks = <&clk_gates0 5>, <&clk_gates0 5>,
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<&clk_gates2 3>, <&clk_gates2 3>,
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<&clk_gates0 5>, <&clk_gates0 5>,
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<&clk_gates2 3>, <&clk_gates2 3>,
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<&clk_gates2 3>, <&clk_gates0 5>,
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<&clk_gates0 5>, <&clk_gates0 5>,
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<&clk_gates2 3>, <&dummy>;
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clock-output-names =
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"gate_pclk_uart0", "gate_pclk_uart1",
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"gate_pclk_uart2", "gate_pclk_uart3",
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"gate_pclk_i2c0", "gate_pclk_i2c1",
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"gate_pclk_i2c2", "gate_pclk_i2c3",
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"gate_pclk_i2c4", "gate_pclk_gpio0",
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"gate_pclk_gpio1", "gate_pclk_gpio2",
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"gate_pclk_gpio3", "gate_aclk_gps";
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#clock-cells = <1>;
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};
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clk_gates9: gate-clk@200000f4 {
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compatible = "rockchip,rk2928-gate-clk";
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reg = <0x200000f4 0x4>;
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clocks = <&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>;
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clock-output-names =
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"gate_clk_core_dbg", "gate_pclk_dbg",
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"gate_clk_trace", "gate_atclk",
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"gate_clk_l2c", "gate_aclk_vio1",
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"gate_pclk_publ", "gate_aclk_gpu";
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#clock-cells = <1>;
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};
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};
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};
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80
arch/arm/boot/dts/rk3188-radxarock.dts
Normal file
80
arch/arm/boot/dts/rk3188-radxarock.dts
Normal file
@ -0,0 +1,80 @@
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/*
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* Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
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*
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
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*/
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/dts-v1/;
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#include "rk3188.dtsi"
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/ {
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model = "Radxa Rock";
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memory {
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reg = <0x60000000 0x80000000>;
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};
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soc {
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uart0: serial@10124000 {
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status = "okay";
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};
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uart1: serial@10126000 {
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status = "okay";
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};
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uart2: serial@20064000 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_xfer>;
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status = "okay";
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};
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uart3: serial@20068000 {
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status = "okay";
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};
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gpio-keys {
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compatible = "gpio-keys";
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#address-cells = <1>;
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#size-cells = <0>;
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autorepeat;
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button@0 {
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gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
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linux,code = <116>;
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label = "GPIO Key Power";
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linux,input-type = <1>;
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gpio-key,wakeup = <1>;
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debounce-interval = <100>;
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};
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};
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gpio-leds {
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compatible = "gpio-leds";
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green {
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gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
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default-state = "off";
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};
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yellow {
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gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
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default-state = "off";
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};
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sleep {
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gpios = <&gpio0 15 0>;
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default-state = "off";
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};
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};
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};
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};
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253
arch/arm/boot/dts/rk3188.dtsi
Normal file
253
arch/arm/boot/dts/rk3188.dtsi
Normal file
@ -0,0 +1,253 @@
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/*
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* Copyright (c) 2013 MundoReader S.L.
|
||||
* Author: Heiko Stuebner <heiko@sntech.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
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|
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include "rk3xxx.dtsi"
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#include "rk3188-clocks.dtsi"
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/ {
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compatible = "rockchip,rk3188";
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|
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cpus {
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#address-cells = <1>;
|
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#size-cells = <0>;
|
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|
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cpu@0 {
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device_type = "cpu";
|
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compatible = "arm,cortex-a9";
|
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next-level-cache = <&L2>;
|
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reg = <0x0>;
|
||||
};
|
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cpu@1 {
|
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device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
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next-level-cache = <&L2>;
|
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reg = <0x1>;
|
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};
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cpu@2 {
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device_type = "cpu";
|
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compatible = "arm,cortex-a9";
|
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next-level-cache = <&L2>;
|
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reg = <0x2>;
|
||||
};
|
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cpu@3 {
|
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device_type = "cpu";
|
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compatible = "arm,cortex-a9";
|
||||
next-level-cache = <&L2>;
|
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reg = <0x3>;
|
||||
};
|
||||
};
|
||||
|
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soc {
|
||||
global-timer@1013c200 {
|
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interrupts = <GIC_PPI 11 0xf04>;
|
||||
};
|
||||
|
||||
local-timer@1013c600 {
|
||||
interrupts = <GIC_PPI 13 0xf04>;
|
||||
};
|
||||
|
||||
pinctrl@20008000 {
|
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compatible = "rockchip,rk3188-pinctrl";
|
||||
reg = <0x20008000 0xa0>,
|
||||
<0x20008164 0x1a0>;
|
||||
reg-names = "base", "pull";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
gpio0: gpio0@0x2000a000 {
|
||||
compatible = "rockchip,rk3188-gpio-bank0";
|
||||
reg = <0x2000a000 0x100>,
|
||||
<0x20004064 0x8>;
|
||||
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk_gates8 9>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio1: gpio1@0x2003c000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x2003c000 0x100>;
|
||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk_gates8 10>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio2@2003e000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x2003e000 0x100>;
|
||||
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk_gates8 11>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio3: gpio3@20080000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x20080000 0x100>;
|
||||
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk_gates8 12>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pcfg_pull_up: pcfg_pull_up {
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pcfg_pull_down: pcfg_pull_down {
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
pcfg_pull_none: pcfg_pull_none {
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
uart0 {
|
||||
uart0_xfer: uart0-xfer {
|
||||
rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart0_cts: uart0-cts {
|
||||
rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart0_rts: uart0-rts {
|
||||
rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart1 {
|
||||
uart1_xfer: uart1-xfer {
|
||||
rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart1_cts: uart1-cts {
|
||||
rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart1_rts: uart1-rts {
|
||||
rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart2 {
|
||||
uart2_xfer: uart2-xfer {
|
||||
rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
/* no rts / cts for uart2 */
|
||||
};
|
||||
|
||||
uart3 {
|
||||
uart3_xfer: uart3-xfer {
|
||||
rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart3_cts: uart3-cts {
|
||||
rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart3_rts: uart3-rts {
|
||||
rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
sd0 {
|
||||
sd0_clk: sd0-clk {
|
||||
rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
sd0_cmd: sd0-cmd {
|
||||
rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
sd0_cd: sd0-cd {
|
||||
rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
sd0_wp: sd0-wp {
|
||||
rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
sd0_pwr: sd0-pwr {
|
||||
rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
sd0_bus1: sd0-bus-width1 {
|
||||
rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
sd0_bus4: sd0-bus-width4 {
|
||||
rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
sd1 {
|
||||
sd1_clk: sd1-clk {
|
||||
rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
sd1_cmd: sd1-cmd {
|
||||
rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
sd1_cd: sd1-cd {
|
||||
rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
sd1_wp: sd1-wp {
|
||||
rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
sd1_bus1: sd1-bus-width1 {
|
||||
rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
sd1_bus4: sd1-bus-width4 {
|
||||
rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user