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clk: exynos4: Add support for SoC-specific register save list
This patch extends suspend/resume support for SoC-specific registers to handle differences in register sets on particular SoCs. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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@ -183,6 +183,26 @@ enum exynos4_clks {
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* list of controller registers to be saved and restored during a
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* suspend/resume cycle.
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*/
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static __initdata unsigned long exynos4210_clk_save[] = {
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E4210_SRC_IMAGE,
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E4210_SRC_LCD1,
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E4210_SRC_MASK_LCD1,
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E4210_DIV_LCD1,
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E4210_GATE_IP_IMAGE,
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E4210_GATE_IP_LCD1,
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E4210_GATE_IP_PERIR,
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E4210_MPLL_CON0,
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};
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static __initdata unsigned long exynos4x12_clk_save[] = {
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E4X12_GATE_IP_IMAGE,
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E4X12_GATE_IP_PERIR,
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E4X12_SRC_CAM1,
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E4X12_DIV_ISP,
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E4X12_DIV_CAM1,
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E4X12_MPLL_CON0,
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};
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static __initdata unsigned long exynos4_clk_regs[] = {
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SRC_LEFTBUS,
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DIV_LEFTBUS,
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@ -986,8 +1006,14 @@ void __init exynos4_clk_init(struct device_node *np)
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panic("%s: unable to determine soc\n", __func__);
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}
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if (exynos4_soc == EXYNOS4210)
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samsung_clk_init(np, reg_base, nr_clks,
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exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs));
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exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
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exynos4210_clk_save, ARRAY_SIZE(exynos4210_clk_save));
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else
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samsung_clk_init(np, reg_base, nr_clks,
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exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
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exynos4x12_clk_save, ARRAY_SIZE(exynos4x12_clk_save));
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if (np)
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samsung_clk_of_register_fixed_ext(exynos4_fixed_rate_ext_clks,
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@ -477,7 +477,8 @@ void __init exynos5250_clk_init(struct device_node *np)
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}
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samsung_clk_init(np, reg_base, nr_clks,
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exynos5250_clk_regs, ARRAY_SIZE(exynos5250_clk_regs));
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exynos5250_clk_regs, ARRAY_SIZE(exynos5250_clk_regs),
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NULL, 0);
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samsung_clk_of_register_fixed_ext(exynos5250_fixed_rate_ext_clks,
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ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
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ext_clk_match);
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@ -115,7 +115,7 @@ void __init exynos5440_clk_init(struct device_node *np)
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return;
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}
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samsung_clk_init(np, reg_base, nr_clks, NULL, 0);
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samsung_clk_init(np, reg_base, nr_clks, NULL, 0, NULL, 0);
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samsung_clk_of_register_fixed_ext(exynos5440_fixed_rate_ext_clks,
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ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match);
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@ -54,7 +54,8 @@ static struct syscore_ops samsung_clk_syscore_ops = {
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/* setup the essentials required to support clock lookup using ccf */
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void __init samsung_clk_init(struct device_node *np, void __iomem *base,
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unsigned long nr_clks, unsigned long *rdump,
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unsigned long nr_rdump)
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unsigned long nr_rdump, unsigned long *soc_rdump,
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unsigned long nr_soc_rdump)
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{
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reg_base = base;
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@ -62,7 +63,7 @@ void __init samsung_clk_init(struct device_node *np, void __iomem *base,
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if (rdump && nr_rdump) {
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unsigned int idx;
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reg_dump = kzalloc(sizeof(struct samsung_clk_reg_dump)
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* nr_rdump, GFP_KERNEL);
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* (nr_rdump + nr_soc_rdump), GFP_KERNEL);
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if (!reg_dump) {
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pr_err("%s: memory alloc for register dump failed\n",
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__func__);
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@ -71,7 +72,9 @@ void __init samsung_clk_init(struct device_node *np, void __iomem *base,
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for (idx = 0; idx < nr_rdump; idx++)
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reg_dump[idx].offset = rdump[idx];
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nr_reg_dump = nr_rdump;
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for (idx = 0; idx < nr_soc_rdump; idx++)
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reg_dump[nr_rdump + idx].offset = soc_rdump[idx];
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nr_reg_dump = nr_rdump + nr_soc_rdump;
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register_syscore_ops(&samsung_clk_syscore_ops);
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}
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#endif
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@ -262,7 +262,8 @@ struct samsung_clk_reg_dump {
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extern void __init samsung_clk_init(struct device_node *np, void __iomem *base,
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unsigned long nr_clks, unsigned long *rdump,
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unsigned long nr_rdump);
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unsigned long nr_rdump, unsigned long *soc_rdump,
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unsigned long nr_soc_rdump);
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extern void __init samsung_clk_of_register_fixed_ext(
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struct samsung_fixed_rate_clock *fixed_rate_clk,
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unsigned int nr_fixed_rate_clk,
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