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ARM cpufreq updates for 6.12
- Several OF related cleanups in cpufreq drivers (Rob Herring). - Enable COMPILE_TEST for ARM drivers (Rob Herrring). - Introduce quirks for syscon failures and use socinfo to get revision for TI cpufreq driver (Dhruva Gole and Nishanth Menon). - Minor cleanups in amd-pstate driver (Anastasia Belova and Dhananjay Ugwekar). - Minor cleanups for loongson, cpufreq-dt and powernv cpufreq drivers (Danila Tikhonov, Huacai Chen, and Liu Jing). -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEx73Crsp7f6M6scA70rkcPK6BEhwFAmbalyoACgkQ0rkcPK6B Ehw9IBAAus+BOdYMzU8VT7j8Y98oOfb5FsJCoTU2KaV2RIIpX4k+6daruCOm0BXP RtRiI+ILV5zLUm8CIC15f2GQE6PtDBFmjky7ItEemcbQPlTkpkZFWNFhBqE1u3hw jllA4p1LmUwAnr1zkwl2CEUJSRJBxWPeTxPL0Ci6pycFhiNPZwGqOreJQRsIMOh3 pgohKSBebxpzgwES8fhR32CqaHphrEFCryHafZIqzsXSBuyETGEKg57zTmdo6ojy GDuaIz6kQ9lKvW/q9iwTih93SsBnzDD85AAERDZkUDxey5IBLztrJLH5QT/XN77K EQOHeygwyKk4su00fXy/LXmMqKHCN/mAHgb6JvWBIm2xbDWx6drBJyV/NdX4YI4w 4m1SqmFH9Cv41UIcynQR83XthGKgIddjEDKPW0GNMQ+LHWlUS6Qm4Kb2q4rXruqD bUWs3NmZEvYD9P2XOKGHgfSPZ0iNXi0Lt5BBIWbeIPNwaikxHisNsNG1W2pMsfke n19cvt20aBJgx2s5acIH7Po8qQglrGGK9EKWRg8gInvtB7QRbHBhXVD6ZNwuIk/7 u2+Y42R4R1GzwsD3EUl+RnnUFgRwhg53OIzcE+AaaMDqGeTdxmG42eg0jGSBA7yx KbljH9PAfsMjjEjsVYReiIYxS28PZNyTBaxZJxD2RyxMz53CV9w= =BlNP -----END PGP SIGNATURE----- Merge tag 'cpufreq-arm-updates-6.12' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/vireshk/pm Merge ARM cpufreq updates for 6.12 from Viresh Kumar: "- Several OF related cleanups in cpufreq drivers (Rob Herring). - Enable COMPILE_TEST for ARM drivers (Rob Herrring). - Introduce quirks for syscon failures and use socinfo to get revision for TI cpufreq driver (Dhruva Gole and Nishanth Menon). - Minor cleanups in amd-pstate driver (Anastasia Belova and Dhananjay Ugwekar). - Minor cleanups for loongson, cpufreq-dt and powernv cpufreq drivers (Danila Tikhonov, Huacai Chen, and Liu Jing)." * tag 'cpufreq-arm-updates-6.12' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/vireshk/pm: cpufreq: ti-cpufreq: Use socinfo to get revision in AM62 family cpufreq: Fix the cacography in powernv-cpufreq.c cpufreq: ti-cpufreq: Introduce quirks to handle syscon fails appropriately cpufreq: loongson3: Use raw_smp_processor_id() in do_service_request() cpufreq: amd-pstate: add check for cpufreq_cpu_get's return value cpufreq: Add SM7325 to cpufreq-dt-platdev blocklist cpufreq: Fix warning on unused of_device_id tables for !CONFIG_OF cpufreq/amd-pstate: Add the missing cpufreq_cpu_put() cpufreq: Drop CONFIG_ARM and CONFIG_ARM64 dependency on Arm drivers cpufreq: Enable COMPILE_TEST on Arm drivers cpufreq: armada-8k: Avoid excessive stack usage cpufreq: omap: Drop asm includes cpufreq: qcom: Add explicit io.h include for readl/writel_relaxed cpufreq: spear: Use of_property_for_each_u32() instead of open coding cpufreq: Use of_property_present()
This commit is contained in:
commit
6af3aab6c7
@ -231,9 +231,7 @@ if X86
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source "drivers/cpufreq/Kconfig.x86"
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endif
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if ARM || ARM64
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source "drivers/cpufreq/Kconfig.arm"
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endif
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if PPC32 || PPC64
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source "drivers/cpufreq/Kconfig.powerpc"
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@ -5,7 +5,7 @@
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config ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM
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tristate "Allwinner nvmem based SUN50I CPUFreq driver"
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depends on ARCH_SUNXI
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depends on ARCH_SUNXI || COMPILE_TEST
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depends on NVMEM_SUNXI_SID
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select PM_OPP
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help
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@ -26,15 +26,17 @@ config ARM_APPLE_SOC_CPUFREQ
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config ARM_ARMADA_37XX_CPUFREQ
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tristate "Armada 37xx CPUFreq support"
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depends on ARCH_MVEBU && CPUFREQ_DT
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depends on ARCH_MVEBU || COMPILE_TEST
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depends on CPUFREQ_DT
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help
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This adds the CPUFreq driver support for Marvell Armada 37xx SoCs.
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The Armada 37xx PMU supports 4 frequency and VDD levels.
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config ARM_ARMADA_8K_CPUFREQ
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tristate "Armada 8K CPUFreq driver"
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depends on ARCH_MVEBU && CPUFREQ_DT
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select ARMADA_AP_CPU_CLK
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depends on ARCH_MVEBU || COMPILE_TEST
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depends on CPUFREQ_DT
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select ARMADA_AP_CPU_CLK if COMMON_CLK
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help
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This enables the CPUFreq driver support for Marvell
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Armada8k SOCs.
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@ -56,7 +58,7 @@ config ARM_SCPI_CPUFREQ
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config ARM_VEXPRESS_SPC_CPUFREQ
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tristate "Versatile Express SPC based CPUfreq driver"
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depends on ARM_CPU_TOPOLOGY && HAVE_CLK
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depends on ARCH_VEXPRESS_SPC
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depends on ARCH_VEXPRESS_SPC || COMPILE_TEST
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select PM_OPP
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help
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This add the CPUfreq driver support for Versatile Express
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@ -75,7 +77,8 @@ config ARM_BRCMSTB_AVS_CPUFREQ
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config ARM_HIGHBANK_CPUFREQ
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tristate "Calxeda Highbank-based"
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depends on ARCH_HIGHBANK && CPUFREQ_DT && REGULATOR
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depends on ARCH_HIGHBANK || COMPILE_TEST
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depends on CPUFREQ_DT && REGULATOR && PL320_MBOX
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default m
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help
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This adds the CPUFreq driver for Calxeda Highbank SoC
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@ -96,7 +99,8 @@ config ARM_IMX6Q_CPUFREQ
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config ARM_IMX_CPUFREQ_DT
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tristate "Freescale i.MX8M cpufreq support"
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depends on ARCH_MXC && CPUFREQ_DT
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depends on CPUFREQ_DT
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depends on ARCH_MXC || COMPILE_TEST
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help
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This adds cpufreq driver support for Freescale i.MX7/i.MX8M
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series SoCs, based on cpufreq-dt.
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@ -111,7 +115,8 @@ config ARM_KIRKWOOD_CPUFREQ
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config ARM_MEDIATEK_CPUFREQ
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tristate "CPU Frequency scaling support for MediaTek SoCs"
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depends on ARCH_MEDIATEK && REGULATOR
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depends on ARCH_MEDIATEK || COMPILE_TEST
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depends on REGULATOR
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select PM_OPP
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help
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This adds the CPUFreq driver support for MediaTek SoCs.
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@ -130,12 +135,12 @@ config ARM_MEDIATEK_CPUFREQ_HW
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config ARM_OMAP2PLUS_CPUFREQ
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bool "TI OMAP2+"
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depends on ARCH_OMAP2PLUS
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depends on ARCH_OMAP2PLUS || COMPILE_TEST
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default ARCH_OMAP2PLUS
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config ARM_QCOM_CPUFREQ_NVMEM
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tristate "Qualcomm nvmem based CPUFreq"
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depends on ARCH_QCOM
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depends on ARCH_QCOM || COMPILE_TEST
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depends on NVMEM_QCOM_QFPROM
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depends on QCOM_SMEM
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select PM_OPP
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@ -166,7 +171,7 @@ config ARM_RASPBERRYPI_CPUFREQ
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config ARM_S3C64XX_CPUFREQ
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bool "Samsung S3C64XX"
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depends on CPU_S3C6410
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depends on CPU_S3C6410 || COMPILE_TEST
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default y
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help
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This adds the CPUFreq driver for Samsung S3C6410 SoC.
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@ -175,7 +180,7 @@ config ARM_S3C64XX_CPUFREQ
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config ARM_S5PV210_CPUFREQ
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bool "Samsung S5PV210 and S5PC110"
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depends on CPU_S5PV210
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depends on CPU_S5PV210 || COMPILE_TEST
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default y
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help
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This adds the CPUFreq driver for Samsung S5PV210 and
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@ -199,14 +204,15 @@ config ARM_SCMI_CPUFREQ
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config ARM_SPEAR_CPUFREQ
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bool "SPEAr CPUFreq support"
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depends on PLAT_SPEAR
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depends on PLAT_SPEAR || COMPILE_TEST
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default y
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help
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This adds the CPUFreq driver support for SPEAr SOCs.
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config ARM_STI_CPUFREQ
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tristate "STi CPUFreq support"
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depends on CPUFREQ_DT && SOC_STIH407
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depends on CPUFREQ_DT
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depends on SOC_STIH407 || COMPILE_TEST
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help
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This driver uses the generic OPP framework to match the running
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platform with a predefined set of suitable values. If not provided
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@ -216,34 +222,38 @@ config ARM_STI_CPUFREQ
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config ARM_TEGRA20_CPUFREQ
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tristate "Tegra20/30 CPUFreq support"
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depends on ARCH_TEGRA && CPUFREQ_DT
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depends on ARCH_TEGRA || COMPILE_TEST
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depends on CPUFREQ_DT
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default y
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help
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This adds the CPUFreq driver support for Tegra20/30 SOCs.
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config ARM_TEGRA124_CPUFREQ
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bool "Tegra124 CPUFreq support"
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depends on ARCH_TEGRA && CPUFREQ_DT
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depends on ARCH_TEGRA || COMPILE_TEST
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depends on CPUFREQ_DT
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default y
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help
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This adds the CPUFreq driver support for Tegra124 SOCs.
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config ARM_TEGRA186_CPUFREQ
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tristate "Tegra186 CPUFreq support"
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depends on ARCH_TEGRA && TEGRA_BPMP
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depends on ARCH_TEGRA || COMPILE_TEST
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depends on TEGRA_BPMP
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help
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This adds the CPUFreq driver support for Tegra186 SOCs.
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config ARM_TEGRA194_CPUFREQ
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tristate "Tegra194 CPUFreq support"
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depends on ARCH_TEGRA_194_SOC && TEGRA_BPMP
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depends on ARCH_TEGRA_194_SOC || (64BIT && COMPILE_TEST)
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depends on TEGRA_BPMP
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default y
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help
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This adds CPU frequency driver support for Tegra194 SOCs.
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config ARM_TI_CPUFREQ
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bool "Texas Instruments CPUFreq support"
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depends on ARCH_OMAP2PLUS || ARCH_K3
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depends on ARCH_OMAP2PLUS || ARCH_K3 || COMPILE_TEST
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default y
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help
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This driver enables valid OPPs on the running platform based on
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@ -255,7 +265,7 @@ config ARM_TI_CPUFREQ
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config ARM_PXA2xx_CPUFREQ
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tristate "Intel PXA2xx CPUfreq driver"
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depends on PXA27x || PXA25x
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depends on PXA27x || PXA25x || COMPILE_TEST
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help
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This add the CPUFreq driver support for Intel PXA2xx SOCs.
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@ -554,12 +554,15 @@ static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf,
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}
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if (value == prev)
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return;
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goto cpufreq_policy_put;
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WRITE_ONCE(cpudata->cppc_req_cached, value);
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amd_pstate_update_perf(cpudata, min_perf, des_perf,
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max_perf, fast_switch);
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cpufreq_policy_put:
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cpufreq_cpu_put(policy);
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}
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static int amd_pstate_verify(struct cpufreq_policy_data *policy)
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@ -656,7 +659,12 @@ static void amd_pstate_adjust_perf(unsigned int cpu,
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unsigned long max_perf, min_perf, des_perf,
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cap_perf, lowest_nonlinear_perf;
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struct cpufreq_policy *policy = cpufreq_cpu_get(cpu);
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struct amd_cpudata *cpudata = policy->driver_data;
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struct amd_cpudata *cpudata;
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if (!policy)
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return;
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cpudata = policy->driver_data;
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if (policy->min != cpudata->min_limit_freq || policy->max != cpudata->max_limit_freq)
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amd_pstate_update_min_max_limit(policy);
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@ -870,11 +878,16 @@ static void amd_pstate_init_prefcore(struct amd_cpudata *cpudata)
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static void amd_pstate_update_limits(unsigned int cpu)
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{
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struct cpufreq_policy *policy = cpufreq_cpu_get(cpu);
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struct amd_cpudata *cpudata = policy->driver_data;
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struct amd_cpudata *cpudata;
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u32 prev_high = 0, cur_high = 0;
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int ret;
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bool highest_perf_changed = false;
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if (!policy)
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return;
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cpudata = policy->driver_data;
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mutex_lock(&amd_pstate_driver_lock);
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if ((!amd_pstate_prefcore) || (!cpudata->hw_prefcore))
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goto free_cpufreq_put;
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@ -85,7 +85,7 @@ static const struct apple_soc_cpufreq_info soc_default_info = {
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.cur_pstate_mask = 0, /* fallback */
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};
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static const struct of_device_id apple_soc_cpufreq_of_match[] = {
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static const struct of_device_id apple_soc_cpufreq_of_match[] __maybe_unused = {
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{
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.compatible = "apple,t8103-cluster-cpufreq",
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.data = &soc_t8103_info,
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@ -132,7 +132,7 @@ static int __init armada_8k_cpufreq_init(void)
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int ret = 0, opps_index = 0, cpu, nb_cpus;
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struct freq_table *freq_tables;
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struct device_node *node;
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struct cpumask cpus;
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static struct cpumask cpus;
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node = of_find_matching_node_and_match(NULL, armada_8k_cpufreq_of_match,
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NULL);
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@ -166,6 +166,7 @@ static const struct of_device_id blocklist[] __initconst = {
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{ .compatible = "qcom,sm6350", },
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{ .compatible = "qcom,sm6375", },
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{ .compatible = "qcom,sm7225", },
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{ .compatible = "qcom,sm7325", },
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{ .compatible = "qcom,sm8150", },
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{ .compatible = "qcom,sm8250", },
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{ .compatible = "qcom,sm8350", },
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@ -69,7 +69,6 @@ static int set_target(struct cpufreq_policy *policy, unsigned int index)
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static const char *find_supply_name(struct device *dev)
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{
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struct device_node *np __free(device_node) = of_node_get(dev->of_node);
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struct property *pp;
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int cpu = dev->id;
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/* This must be valid for sure */
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@ -77,14 +76,10 @@ static const char *find_supply_name(struct device *dev)
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return NULL;
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/* Try "cpu0" for older DTs */
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if (!cpu) {
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pp = of_find_property(np, "cpu0-supply", NULL);
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if (pp)
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return "cpu0";
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}
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if (!cpu && of_property_present(np, "cpu0-supply"))
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return "cpu0";
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pp = of_find_property(np, "cpu-supply", NULL);
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if (pp)
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if (of_property_present(np, "cpu-supply"))
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return "cpu";
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dev_dbg(dev, "no regulator for cpu%d\n", cpu);
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|
@ -176,7 +176,7 @@ static DEFINE_PER_CPU(struct loongson3_freq_data *, freq_data);
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static inline int do_service_request(u32 id, u32 info, u32 cmd, u32 val, u32 extra)
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{
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int retries;
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unsigned int cpu = smp_processor_id();
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unsigned int cpu = raw_smp_processor_id();
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unsigned int package = cpu_data[cpu].package;
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union smc_message msg, last;
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|
@ -738,7 +738,7 @@ static const struct mtk_cpufreq_platform_data mt8516_platform_data = {
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};
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/* List of machines supported by this driver */
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static const struct of_device_id mtk_cpufreq_machines[] __initconst = {
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static const struct of_device_id mtk_cpufreq_machines[] __initconst __maybe_unused = {
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{ .compatible = "mediatek,mt2701", .data = &mt2701_platform_data },
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{ .compatible = "mediatek,mt2712", .data = &mt2701_platform_data },
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{ .compatible = "mediatek,mt7622", .data = &mt7622_platform_data },
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|
@ -28,9 +28,6 @@
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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|
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#include <asm/smp_plat.h>
|
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#include <asm/cpu.h>
|
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|
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/* OPP tolerance in percentage */
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#define OPP_TOLERANCE 4
|
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|
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|
@ -505,7 +505,7 @@ static int __init g5_pm72_cpufreq_init(struct device_node *cpunode)
|
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continue;
|
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if (strcmp(loc, "CPU CLOCK"))
|
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continue;
|
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if (!of_get_property(hwclock, "platform-get-frequency", NULL))
|
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if (!of_property_present(hwclock, "platform-get-frequency"))
|
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continue;
|
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break;
|
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}
|
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|
@ -692,7 +692,7 @@ static void gpstate_timer_handler(struct timer_list *t)
|
||||
}
|
||||
|
||||
/*
|
||||
* If PMCR was last updated was using fast_swtich then
|
||||
* If PMCR was last updated was using fast_switch then
|
||||
* We may have wrong in gpstate->last_lpstate_idx
|
||||
* value. Hence, read from PMCR to get correct data.
|
||||
*/
|
||||
|
@ -9,6 +9,7 @@
|
||||
#include <linux/init.h>
|
||||
#include <linux/interconnect.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
|
@ -611,7 +611,7 @@ static struct platform_driver qcom_cpufreq_driver = {
|
||||
},
|
||||
};
|
||||
|
||||
static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
|
||||
static const struct of_device_id qcom_cpufreq_match_list[] __initconst __maybe_unused = {
|
||||
{ .compatible = "qcom,apq8096", .data = &match_data_kryo },
|
||||
{ .compatible = "qcom,msm8909", .data = &match_data_msm8909 },
|
||||
{ .compatible = "qcom,msm8996", .data = &match_data_kryo },
|
||||
|
@ -171,10 +171,9 @@ static struct cpufreq_driver spear_cpufreq_driver = {
|
||||
static int spear_cpufreq_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np;
|
||||
const struct property *prop;
|
||||
struct cpufreq_frequency_table *freq_tbl;
|
||||
const __be32 *val;
|
||||
int cnt, i, ret;
|
||||
u32 val;
|
||||
int cnt, ret, i = 0;
|
||||
|
||||
np = of_cpu_device_node_get(0);
|
||||
if (!np) {
|
||||
@ -186,26 +185,23 @@ static int spear_cpufreq_probe(struct platform_device *pdev)
|
||||
&spear_cpufreq.transition_latency))
|
||||
spear_cpufreq.transition_latency = CPUFREQ_ETERNAL;
|
||||
|
||||
prop = of_find_property(np, "cpufreq_tbl", NULL);
|
||||
if (!prop || !prop->value) {
|
||||
cnt = of_property_count_u32_elems(np, "cpufreq_tbl");
|
||||
if (cnt <= 0) {
|
||||
pr_err("Invalid cpufreq_tbl\n");
|
||||
ret = -ENODEV;
|
||||
goto out_put_node;
|
||||
}
|
||||
|
||||
cnt = prop->length / sizeof(u32);
|
||||
val = prop->value;
|
||||
|
||||
freq_tbl = kcalloc(cnt + 1, sizeof(*freq_tbl), GFP_KERNEL);
|
||||
if (!freq_tbl) {
|
||||
ret = -ENOMEM;
|
||||
goto out_put_node;
|
||||
}
|
||||
|
||||
for (i = 0; i < cnt; i++)
|
||||
freq_tbl[i].frequency = be32_to_cpup(val++);
|
||||
of_property_for_each_u32(np, "cpufreq_tbl", val)
|
||||
freq_tbl[i++].frequency = val;
|
||||
|
||||
freq_tbl[i].frequency = CPUFREQ_TABLE_END;
|
||||
freq_tbl[cnt].frequency = CPUFREQ_TABLE_END;
|
||||
|
||||
spear_cpufreq.freq_tbl = freq_tbl;
|
||||
|
||||
|
@ -267,7 +267,7 @@ static int __init sti_cpufreq_init(void)
|
||||
goto skip_voltage_scaling;
|
||||
}
|
||||
|
||||
if (!of_get_property(ddata.cpu->of_node, "operating-points-v2", NULL)) {
|
||||
if (!of_property_present(ddata.cpu->of_node, "operating-points-v2")) {
|
||||
dev_err(ddata.cpu, "OPP-v2 not supported\n");
|
||||
goto skip_voltage_scaling;
|
||||
}
|
||||
|
@ -146,7 +146,7 @@ static bool dt_has_supported_hw(void)
|
||||
return false;
|
||||
|
||||
for_each_child_of_node_scoped(np, opp) {
|
||||
if (of_find_property(opp, "opp-supported-hw", NULL)) {
|
||||
if (of_property_present(opp, "opp-supported-hw")) {
|
||||
has_opp_supported_hw = true;
|
||||
break;
|
||||
}
|
||||
|
@ -16,6 +16,7 @@
|
||||
#include <linux/pm_opp.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/sys_soc.h>
|
||||
|
||||
#define REVISION_MASK 0xF
|
||||
#define REVISION_SHIFT 28
|
||||
@ -90,6 +91,9 @@ struct ti_cpufreq_soc_data {
|
||||
unsigned long efuse_shift;
|
||||
unsigned long rev_offset;
|
||||
bool multi_regulator;
|
||||
/* Backward compatibility hack: Might have missing syscon */
|
||||
#define TI_QUIRK_SYSCON_MAY_BE_MISSING 0x1
|
||||
u8 quirks;
|
||||
};
|
||||
|
||||
struct ti_cpufreq_data {
|
||||
@ -254,6 +258,7 @@ static struct ti_cpufreq_soc_data omap34xx_soc_data = {
|
||||
.efuse_mask = BIT(3),
|
||||
.rev_offset = OMAP3_CONTROL_IDCODE - OMAP3_SYSCON_BASE,
|
||||
.multi_regulator = false,
|
||||
.quirks = TI_QUIRK_SYSCON_MAY_BE_MISSING,
|
||||
};
|
||||
|
||||
/*
|
||||
@ -281,6 +286,7 @@ static struct ti_cpufreq_soc_data omap36xx_soc_data = {
|
||||
.efuse_mask = BIT(9),
|
||||
.rev_offset = OMAP3_CONTROL_IDCODE - OMAP3_SYSCON_BASE,
|
||||
.multi_regulator = true,
|
||||
.quirks = TI_QUIRK_SYSCON_MAY_BE_MISSING,
|
||||
};
|
||||
|
||||
/*
|
||||
@ -295,6 +301,14 @@ static struct ti_cpufreq_soc_data am3517_soc_data = {
|
||||
.efuse_mask = 0,
|
||||
.rev_offset = OMAP3_CONTROL_IDCODE - OMAP3_SYSCON_BASE,
|
||||
.multi_regulator = false,
|
||||
.quirks = TI_QUIRK_SYSCON_MAY_BE_MISSING,
|
||||
};
|
||||
|
||||
static const struct soc_device_attribute k3_cpufreq_soc[] = {
|
||||
{ .family = "AM62X", .revision = "SR1.0" },
|
||||
{ .family = "AM62AX", .revision = "SR1.0" },
|
||||
{ .family = "AM62PX", .revision = "SR1.0" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static struct ti_cpufreq_soc_data am625_soc_data = {
|
||||
@ -340,7 +354,7 @@ static int ti_cpufreq_get_efuse(struct ti_cpufreq_data *opp_data,
|
||||
|
||||
ret = regmap_read(opp_data->syscon, opp_data->soc_data->efuse_offset,
|
||||
&efuse);
|
||||
if (ret == -EIO) {
|
||||
if (opp_data->soc_data->quirks & TI_QUIRK_SYSCON_MAY_BE_MISSING && ret == -EIO) {
|
||||
/* not a syscon register! */
|
||||
void __iomem *regs = ioremap(OMAP3_SYSCON_BASE +
|
||||
opp_data->soc_data->efuse_offset, 4);
|
||||
@ -378,10 +392,20 @@ static int ti_cpufreq_get_rev(struct ti_cpufreq_data *opp_data,
|
||||
struct device *dev = opp_data->cpu_dev;
|
||||
u32 revision;
|
||||
int ret;
|
||||
if (soc_device_match(k3_cpufreq_soc)) {
|
||||
/*
|
||||
* Since the SR is 1.0, hard code the revision_value as
|
||||
* 0x1 here. This way we avoid re using the same register
|
||||
* that is giving us required information inside socinfo
|
||||
* anyway.
|
||||
*/
|
||||
*revision_value = 0x1;
|
||||
goto done;
|
||||
}
|
||||
|
||||
ret = regmap_read(opp_data->syscon, opp_data->soc_data->rev_offset,
|
||||
&revision);
|
||||
if (ret == -EIO) {
|
||||
if (opp_data->soc_data->quirks & TI_QUIRK_SYSCON_MAY_BE_MISSING && ret == -EIO) {
|
||||
/* not a syscon register! */
|
||||
void __iomem *regs = ioremap(OMAP3_SYSCON_BASE +
|
||||
opp_data->soc_data->rev_offset, 4);
|
||||
@ -400,6 +424,7 @@ static int ti_cpufreq_get_rev(struct ti_cpufreq_data *opp_data,
|
||||
|
||||
*revision_value = BIT((revision >> REVISION_SHIFT) & REVISION_MASK);
|
||||
|
||||
done:
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -419,7 +444,7 @@ static int ti_cpufreq_setup_syscon_register(struct ti_cpufreq_data *opp_data)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id ti_cpufreq_of_match[] = {
|
||||
static const struct of_device_id ti_cpufreq_of_match[] __maybe_unused = {
|
||||
{ .compatible = "ti,am33xx", .data = &am3x_soc_data, },
|
||||
{ .compatible = "ti,am3517", .data = &am3517_soc_data, },
|
||||
{ .compatible = "ti,am43", .data = &am4x_soc_data, },
|
||||
|
Loading…
Reference in New Issue
Block a user