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Second Round of Renesas ARM Based SoC DT Updates for v4.15

Browse Source 
* r8a77430 (RZ/G1M) SoC
   - Add XHCI support to SoC DT. Boards may enable this as appropriate
 
 * All Renesas ARM based SoCs
   - Add missing clocks for ARM CPU cores
 
     Geert Uytterhoeven says "This series improves DT hardware descriptions
     for Renesas arm32 SoCs by adding missing clocks properties to the
     device nodes corresponding to ARM CPU cores."
 
 * R-Car Gen 1 and 2, and RZ/G SoCs
   - Use R-Car Fallback compat strings for GPIO
 
     Simon Horman says "Use newly added R-Car GPIO Gen 1, 2 and 3 fallback
     compat strings in peace of now deprecated non-generation specific R-Car
     GPIO fallback compat string in the DT of Renesas ARM and arm64 based
     SoCs.
 
     As noted in the changelogs for the r8a777[89] changes, this introduces
     an incompatibility with pre-v4.14 kernels used with new DTBs. There is
     no run-time effect for other SoCs updated by this changeset."
 
 * r7s72100 (RZ/A1H) GR-Peach board
   - Add pin configuration subnode for ETHER pin group.
     This avoids relying on boot-loader configuration of these pins.
 
   - Enable ostm0 and ostm1 timers
 
     Jacopo Mondi says these are "to be used as clock source and clockevent
     source. The timers provides greater accuracy than the already enabled
     mtu2 one."
 
   - Correct leds node name indent
 
   - Enable MTU2 timer pulse unit
 
    Jacopo Mondi says "MTU2 multi-function/multi-channel timer/counter is
    not enabled for GR-Peach board. The timer is used as clock event source
    to schedule wake-ups, and without this enabled all sleeps not performed
    through busy waiting hang the board."
 
 * r8a7743 (RZ/G1M) iW-RainboW-G20M-Qseven SoM
   - Add USB function support
 
 * r8a7745 (RZ/G1E) iW-RainboW-G22D development platform
   - Add USB2.0 Host support
 
 * r8a7743 (RZ/G1M) iW-RainboW-G20D-Qseven development platform
   - Rework DT architecture and add DT for camera DB
 
     Fabrizio Castro says "Some of the serial interfaces are exposed on the
     camera daughter board.  The camera daughter board can be connected to
     the carrier board by means of expansion connectors 1, 2 and 3. The
     carrier board may host an RZ/G1M or an RZ/G1N based SoM.
 
     While adding support for the serial interfaces on the camera daughter
     board we faced the dilemma of how to properly describe all of the
     possible HW configurations and how to maximize code reuse.
 
     The best option would be to use device tree overlays, however there is
     still some work to be done on that front before actually using them,
     therefore for the time being we decided to provide .dtsi files to
     describe the carrier board and the camera daughter board, and provide
     .dts files to describe the HW configurations we need to support."
 
 * r8a779[0-4] R-Car Gen2 SoCs
   - Use generic node name for VSP1 nodes
 
     Geert Uytterhoeven says "This patch series replaces the specific node
     names used for the VSP1 nodes by the preferred generic node names, cfr.
     commit 0e1bfb72b0 ("v4l: vsp1: Use generic node name")."
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Merge tag 'renesas-dt2-for-v4.15' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Pull "Second Round of Renesas ARM Based SoC DT Updates for v4.15" from Simon Horman:

* r8a77430 (RZ/G1M) SoC
  - Add XHCI support to SoC DT. Boards may enable this as appropriate

* All Renesas ARM based SoCs
  - Add missing clocks for ARM CPU cores

    Geert Uytterhoeven says "This series improves DT hardware descriptions
    for Renesas arm32 SoCs by adding missing clocks properties to the
    device nodes corresponding to ARM CPU cores."

* R-Car Gen 1 and 2, and RZ/G SoCs
  - Use R-Car Fallback compat strings for GPIO

    Simon Horman says "Use newly added R-Car GPIO Gen 1, 2 and 3 fallback
    compat strings in peace of now deprecated non-generation specific R-Car
    GPIO fallback compat string in the DT of Renesas ARM and arm64 based
    SoCs.

    As noted in the changelogs for the r8a777[89] changes, this introduces
    an incompatibility with pre-v4.14 kernels used with new DTBs. There is
    no run-time effect for other SoCs updated by this changeset."

* r7s72100 (RZ/A1H) GR-Peach board
  - Add pin configuration subnode for ETHER pin group.
    This avoids relying on boot-loader configuration of these pins.

  - Enable ostm0 and ostm1 timers

    Jacopo Mondi says these are "to be used as clock source and clockevent
    source. The timers provides greater accuracy than the already enabled
    mtu2 one."

  - Correct leds node name indent

  - Enable MTU2 timer pulse unit

   Jacopo Mondi says "MTU2 multi-function/multi-channel timer/counter is
   not enabled for GR-Peach board. The timer is used as clock event source
   to schedule wake-ups, and without this enabled all sleeps not performed
   through busy waiting hang the board."

* r8a7743 (RZ/G1M) iW-RainboW-G20M-Qseven SoM
  - Add USB function support

* r8a7745 (RZ/G1E) iW-RainboW-G22D development platform
  - Add USB2.0 Host support

* r8a7743 (RZ/G1M) iW-RainboW-G20D-Qseven development platform
  - Rework DT architecture and add DT for camera DB

    Fabrizio Castro says "Some of the serial interfaces are exposed on the
    camera daughter board.  The camera daughter board can be connected to
    the carrier board by means of expansion connectors 1, 2 and 3. The
    carrier board may host an RZ/G1M or an RZ/G1N based SoM.

    While adding support for the serial interfaces on the camera daughter
    board we faced the dilemma of how to properly describe all of the
    possible HW configurations and how to maximize code reuse.

    The best option would be to use device tree overlays, however there is
    still some work to be done on that front before actually using them,
    therefore for the time being we decided to provide .dtsi files to
    describe the carrier board and the camera daughter board, and provide
    .dts files to describe the HW configurations we need to support."

* r8a779[0-4] R-Car Gen2 SoCs
  - Use generic node name for VSP1 nodes

    Geert Uytterhoeven says "This patch series replaces the specific node
    names used for the VSP1 nodes by the preferred generic node names, cfr.
    commit 0e1bfb72b0 ("v4l: vsp1: Use generic node name")."

* tag 'renesas-dt2-for-v4.15' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (42 commits)
  ARM: dts: r8a7743: Add xhci support to SoC dtsi
  ARM: dts: r7s72100: Add clock for CA9 CPU core
  dt-bindings: clk: r7s72100: Add missing I and G clocks
  ARM: dts: sh73a0: Add clocks for CA9 CPU cores
  ARM: dts: r8a7794: Add missing clock for secondary CA7 CPU core
  ARM: dts: r8a7793: Add missing clock for secondary CA15 CPU core
  ARM: dts: r8a7792: Add missing clock for secondary CA15 CPU core
  ARM: dts: r8a7791: Add missing clock for secondary CA15 CPU core
  ARM: dts: r8a7790: Add clocks for CA7 CPU cores
  ARM: dts: r8a7790: Add missing clocks for secondary CA15 CPU cores
  ARM: dts: r8a7779: Add clocks for CA9 CPU cores
  ARM: dts: r8a7778: Add clock for CA9 CPU core
  ARM: dts: r8a7743: Add missing clock for secondary CA15 CPU core
  ARM: dts: r8a73a4: Add clock for CA15 CPU0 core
  ARM: dts: r8a7794: Use R-Car GPIO Gen2 fallback compat string
  ARM: dts: r8a7793: Use R-Car GPIO Gen2 fallback compat string
  ARM: dts: r8a7792: Use R-Car GPIO Gen2 fallback compat string
  ARM: dts: r8a7791: Use R-Car GPIO Gen2 fallback compat string
  ARM: dts: r8a7790: Use R-Car GPIO Gen2 fallback compat string
  ARM: dts: r8a7743: Use R-Car GPIO Gen2 fallback compat string
  ...
This commit is contained in:
Arnd Bergmann 2017-10-30 12:02:31 +01:00
commit 6ac5482ee6
20 changed files with 545 additions and 211 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/boot/dts/Makefile
View File

@ -727,6 +727,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
r8a73a4-ape6evm.dtb \
r8a7740-armadillo800eva.dtb \
r8a7743-iwg20d-q7.dtb \
r8a7743-iwg20d-q7-dbcm-ca.dtb \
r8a7743-sk-rzg1m.dtb \
r8a7745-iwg22d-sodimm.dtb \
r8a7745-sk-rzg1e.dtb \

152
arch/arm/boot/dts/iwg20d-q7-common.dtsi Normal file
View File

@ -0,0 +1,152 @@
/*
* Device Tree Source for the iWave-RZ/G1M/G1N Qseven carrier board
*
* Copyright (C) 2017 Renesas Electronics Corp.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/ {
aliases {
serial0 = &scif0;
ethernet0 = &avb;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = "serial0:115200n8";
};
vcc_sdhi1: regulator-vcc-sdhi1 {
compatible = "regulator-fixed";
regulator-name = "SDHI1 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 16 GPIO_ACTIVE_LOW>;
};
vccq_sdhi1: regulator-vccq-sdhi1 {
compatible = "regulator-gpio";
regulator-name = "SDHI1 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
};
};
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
phy-handle = <&phy3>;
phy-mode = "gmii";
renesas,no-ether-link;
status = "okay";
phy3: ethernet-phy@3 {
reg = <3>;
micrel,led-mode = <1>;
};
};
&hsusb {
status = "okay";
pinctrl-0 = <&usb0_pins>;
pinctrl-names = "default";
};
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
rtc@68 {
compatible = "ti,bq32000";
reg = <0x68>;
};
};
&pci0 {
pinctrl-0 = <&usb0_pins>;
pinctrl-names = "default";
};
&pci1 {
status = "okay";
pinctrl-0 = <&usb1_pins>;
pinctrl-names = "default";
};
&pfc {
avb_pins: avb {
groups = "avb_mdio", "avb_gmii";
function = "avb";
};
i2c2_pins: i2c2 {
groups = "i2c2";
function = "i2c2";
};
scif0_pins: scif0 {
groups = "scif0_data_d";
function = "scif0";
};
sdhi1_pins: sd1 {
groups = "sdhi1_data4", "sdhi1_ctrl";
function = "sdhi1";
power-source = <3300>;
};
sdhi1_pins_uhs: sd1_uhs {
groups = "sdhi1_data4", "sdhi1_ctrl";
function = "sdhi1";
power-source = <1800>;
};
usb0_pins: usb0 {
groups = "usb0";
function = "usb0";
};
usb1_pins: usb1 {
groups = "usb1";
function = "usb1";
};
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
status = "okay";
};
&sdhi1 {
pinctrl-0 = <&sdhi1_pins>;
pinctrl-1 = <&sdhi1_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi1>;
vqmmc-supply = <&vccq_sdhi1>;
cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
sd-uhs-sdr50;
status = "okay";
};
&usbphy {
status = "okay";
};

43
arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi Normal file
View File

@ -0,0 +1,43 @@
/*
* Device Tree Source for the iWave-RZ-G1M/N Daughter Board Camera Module
*
* Copyright (C) 2017 Renesas Electronics Corp.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/ {
aliases {
serial1 = &scif1;
serial4 = &hscif1;
};
};
&hscif1 {
pinctrl-0 = <&hscif1_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&pfc {
hscif1_pins: hscif1 {
groups = "hscif1_data_c", "hscif1_ctrl_c";
function = "hscif1";
};
scif1_pins: scif1 {
groups = "scif1_data_d";
function = "scif1";
};
};
&scif1 {
pinctrl-0 = <&scif1_pins>;
pinctrl-names = "default";
status = "okay";
};

53
arch/arm/boot/dts/r7s72100-gr-peach.dts
View File

@ -53,7 +53,7 @@
};
};
leds {
leds {
status = "okay";
compatible = "gpio-leds";
@ -68,6 +68,28 @@ leds {
/* P6_2 as RxD2; P6_3 as TxD2 */
pinmux = <RZA1_PINMUX(6, 2, 7)>, <RZA1_PINMUX(6, 3, 7)>;
};
ether_pins: ether {
/* Ethernet on Ports 1,3,5,10 */
pinmux = <RZA1_PINMUX(1, 14, 4)>, /* P1_14 = ET_COL */
<RZA1_PINMUX(3, 0, 2)>, /* P3_0 = ET_TXCLK */
<RZA1_PINMUX(3, 3, 2)>, /* P3_3 = ET_MDIO */
<RZA1_PINMUX(3, 4, 2)>, /* P3_4 = ET_RXCLK */
<RZA1_PINMUX(3, 5, 2)>, /* P3_5 = ET_RXER */
<RZA1_PINMUX(3, 6, 2)>, /* P3_6 = ET_RXDV */
<RZA1_PINMUX(5, 9, 2)>, /* P5_9 = ET_MDC */
<RZA1_PINMUX(10, 1, 4)>, /* P10_1 = ET_TXER */
<RZA1_PINMUX(10, 2, 4)>, /* P10_2 = ET_TXEN */
<RZA1_PINMUX(10, 3, 4)>, /* P10_3 = ET_CRS */
<RZA1_PINMUX(10, 4, 4)>, /* P10_4 = ET_TXD0 */
<RZA1_PINMUX(10, 5, 4)>, /* P10_5 = ET_TXD1 */
<RZA1_PINMUX(10, 6, 4)>, /* P10_6 = ET_TXD2 */
<RZA1_PINMUX(10, 7, 4)>, /* P10_7 = ET_TXD3 */
<RZA1_PINMUX(10, 8, 4)>, /* P10_8 = ET_RXD0 */
<RZA1_PINMUX(10, 9, 4)>, /* P10_9 = ET_RXD1 */
<RZA1_PINMUX(10, 10, 4)>,/* P10_10 = ET_RXD2 */
<RZA1_PINMUX(10, 11, 4)>;/* P10_11 = ET_RXD3 */
};
};
&extal_clk {
@ -78,9 +100,38 @@ leds {
clock-frequency = <48000000>;
};
&mtu2 {
status = "okay";
};
&ostm0 {
status = "okay";
};
&ostm1 {
status = "okay";
};
&scif2 {
pinctrl-names = "default";
pinctrl-0 = <&scif2_pins>;
status = "okay";
};
&ether {
pinctrl-names = "default";
pinctrl-0 = <&ether_pins>;
status = "okay";
renesas,no-ether-link;
phy-handle = <&phy0>;
phy0: ethernet-phy@0 {
reg = <0>;
reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>;
reset-delay-us = <5>;
};
};

1
arch/arm/boot/dts/r7s72100.dtsi
View File

@ -203,6 +203,7 @@
compatible = "arm,cortex-a9";
reg = <0>;
clock-frequency = <400000000>;
clocks = <&cpg_clocks R7S72100_CLK_I>;
next-level-cache = <&L2>;
};
};

1
arch/arm/boot/dts/r8a73a4.dtsi
View File

@ -27,6 +27,7 @@
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0>;
clocks = <&cpg_clocks R8A73A4_CLK_Z>;
clock-frequency = <1500000000>;
power-domains = <&pd_a2sl>;
next-level-cache = <&L2_CA15>;

19
arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts Normal file
View File

@ -0,0 +1,19 @@
/*
* Device Tree Source for the iWave-RZ/G1M Qseven board + camera daughter board
*
* Copyright (C) 2017 Renesas Electronics Corp.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/dts-v1/;
#include "r8a7743-iwg20m.dtsi"
#include "iwg20d-q7-common.dtsi"
#include "iwg20d-q7-dbcm-ca.dtsi"
/ {
model = "iW-RainboW-G20D-Q7 RZ/G1M based plus camera daughter board";
compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743";
};

139
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
View File

@ -1,5 +1,5 @@
/*
* Device Tree Source for the iWave-RZG1M Qseven carrier board
* Device Tree Source for the iWave-RZ/G1M Qseven board
*
* Copyright (C) 2017 Renesas Electronics Corp.
*
@ -10,144 +10,9 @@
/dts-v1/;
#include "r8a7743-iwg20m.dtsi"
#include "iwg20d-q7-common.dtsi"
/ {
model = "iWave Systems RainboW-G20D-Qseven board based on RZ/G1M";
compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743";
aliases {
serial0 = &scif0;
ethernet0 = &avb;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = "serial0:115200n8";
};
vcc_sdhi1: regulator-vcc-sdhi1 {
compatible = "regulator-fixed";
regulator-name = "SDHI1 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 16 GPIO_ACTIVE_LOW>;
};
vccq_sdhi1: regulator-vccq-sdhi1 {
compatible = "regulator-gpio";
regulator-name = "SDHI1 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
};
};
&pfc {
i2c2_pins: i2c2 {
groups = "i2c2";
function = "i2c2";
};
scif0_pins: scif0 {
groups = "scif0_data_d";
function = "scif0";
};
avb_pins: avb {
groups = "avb_mdio", "avb_gmii";
function = "avb";
};
sdhi1_pins: sd1 {
groups = "sdhi1_data4", "sdhi1_ctrl";
function = "sdhi1";
power-source = <3300>;
};
sdhi1_pins_uhs: sd1_uhs {
groups = "sdhi1_data4", "sdhi1_ctrl";
function = "sdhi1";
power-source = <1800>;
};
usb0_pins: usb0 {
groups = "usb0";
function = "usb0";
};
usb1_pins: usb1 {
groups = "usb1";
function = "usb1";
};
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
status = "okay";
};
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
phy-handle = <&phy3>;
phy-mode = "gmii";
renesas,no-ether-link;
status = "okay";
phy3: ethernet-phy@3 {
reg = <3>;
micrel,led-mode = <1>;
};
};
&sdhi1 {
pinctrl-0 = <&sdhi1_pins>;
pinctrl-1 = <&sdhi1_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi1>;
vqmmc-supply = <&vccq_sdhi1>;
cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
sd-uhs-sdr50;
status = "okay";
};
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
rtc@68 {
compatible = "ti,bq32000";
reg = <0x68>;
};
};
&pci0 {
status = "okay";
pinctrl-0 = <&usb0_pins>;
pinctrl-names = "default";
};
&pci1 {
status = "okay";
pinctrl-0 = <&usb1_pins>;
pinctrl-names = "default";
};
&usbphy {
status = "okay";
};

82
arch/arm/boot/dts/r8a7743.dtsi
View File

@ -63,6 +63,7 @@
compatible = "arm,cortex-a15";
reg = <1>;
clock-frequency = <1500000000>;
clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
power-domains = <&sysc R8A7743_PD_CA15_CPU1>;
next-level-cache = <&L2_CA15>;
};
@ -108,7 +109,7 @@
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a7743",
"renesas,gpio-rcar";
"renesas,rcar-gen2-gpio";
reg = <0 0xe6050000 0 0x50>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -123,7 +124,7 @@
gpio1: gpio@e6051000 {
compatible = "renesas,gpio-r8a7743",
"renesas,gpio-rcar";
"renesas,rcar-gen2-gpio";
reg = <0 0xe6051000 0 0x50>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -138,7 +139,7 @@
gpio2: gpio@e6052000 {
compatible = "renesas,gpio-r8a7743",
"renesas,gpio-rcar";
"renesas,rcar-gen2-gpio";
reg = <0 0xe6052000 0 0x50>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -153,7 +154,7 @@
gpio3: gpio@e6053000 {
compatible = "renesas,gpio-r8a7743",
"renesas,gpio-rcar";
"renesas,rcar-gen2-gpio";
reg = <0 0xe6053000 0 0x50>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -168,7 +169,7 @@
gpio4: gpio@e6054000 {
compatible = "renesas,gpio-r8a7743",
"renesas,gpio-rcar";
"renesas,rcar-gen2-gpio";
reg = <0 0xe6054000 0 0x50>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -183,7 +184,7 @@
gpio5: gpio@e6055000 {
compatible = "renesas,gpio-r8a7743",
"renesas,gpio-rcar";
"renesas,rcar-gen2-gpio";
reg = <0 0xe6055000 0 0x50>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -198,7 +199,7 @@
gpio6: gpio@e6055400 {
compatible = "renesas,gpio-r8a7743",
"renesas,gpio-rcar";
"renesas,rcar-gen2-gpio";
reg = <0 0xe6055400 0 0x50>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -213,7 +214,7 @@
gpio7: gpio@e6055800 {
compatible = "renesas,gpio-r8a7743",
"renesas,gpio-rcar";
"renesas,rcar-gen2-gpio";
reg = <0 0xe6055800 0 0x50>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -355,6 +356,34 @@
dma-channels = <15>;
};
usb_dmac0: dma-controller@e65a0000 {
compatible = "renesas,r8a7743-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65a0000 0 0x100>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 330>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 330>;
#dma-cells = <1>;
dma-channels = <2>;
};
usb_dmac1: dma-controller@e65b0000 {
compatible = "renesas,r8a7743-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65b0000 0 0x100>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 331>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 331>;
#dma-cells = <1>;
dma-channels = <2>;
};
/* The memory map in the User's Manual maps the cores to bus
* numbers
*/
@ -903,6 +932,26 @@
status = "disabled";
};
/*
* pci1 and xhci share the same phy, therefore only one of them
* can be active at any one time. If both of them are enabled,
* a race condition will determine who'll control the phy.
* A firmware file is needed by the xhci driver in order for
* USB 3.0 to work properly.
*/
xhci: usb@ee000000 {
compatible = "renesas,xhci-r8a7743",
"renesas,rcar-gen2-xhci";
reg = <0 0xee000000 0 0xc00>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 328>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 328>;
phys = <&usb2 1>;
phy-names = "usb";
status = "disabled";
};
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a7743";
reg = <0 0xee100000 0 0x328>;
@ -945,6 +994,23 @@
status = "disabled";
};
hsusb: usb@e6590000 {
compatible = "renesas,usbhs-r8a7743",
"renesas,rcar-gen2-usbhs";
reg = <0 0xe6590000 0 0x100>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 704>;
dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
<&usb_dmac1 0>, <&usb_dmac1 1>;
dma-names = "ch0", "ch1", "ch2", "ch3";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 704>;
renesas,buswait = <4>;
phys = <&usb0 1>;
phy-names = "usb";
status = "disabled";
};
usbphy: usb-phy@e6590100 {
compatible = "renesas,usb-phy-r8a7743",
"renesas,rcar-gen2-usb-phy";

15
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
View File

@ -55,6 +55,11 @@
function = "sdhi0";
power-source = <3300>;
};
usb1_pins: usb1 {
groups = "usb1";
function = "usb1";
};
};
&scif4 {
@ -92,3 +97,13 @@
cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pci1 {
status = "okay";
pinctrl-0 = <&usb1_pins>;
pinctrl-names = "default";
};
&usbphy {
status = "okay";
};

92
arch/arm/boot/dts/r8a7745.dtsi
View File

@ -845,6 +845,98 @@
resets = <&cpg 311>;
status = "disabled";
};
pci0: pci@ee090000 {
compatible = "renesas,pci-r8a7745",
"renesas,pci-rcar-gen2";
device_type = "pci";
reg = <0 0xee090000 0 0xc00>,
<0 0xee080000 0 0x1100>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>;
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 703>;
status = "disabled";
bus-range = <0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
interrupt-map-mask = <0xff00 0 0 0x7>;
interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
usb@1,0 {
reg = <0x800 0 0 0 0>;
phys = <&usb0 0>;
phy-names = "usb";
};
usb@2,0 {
reg = <0x1000 0 0 0 0>;
phys = <&usb0 0>;
phy-names = "usb";
};
};
pci1: pci@ee0d0000 {
compatible = "renesas,pci-r8a7745",
"renesas,pci-rcar-gen2";
device_type = "pci";
reg = <0 0xee0d0000 0 0xc00>,
<0 0xee0c0000 0 0x1100>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>;
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 703>;
status = "disabled";
bus-range = <1 1>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
interrupt-map-mask = <0xff00 0 0 0x7>;
interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
usb@1,0 {
reg = <0x10800 0 0 0 0>;
phys = <&usb2 0>;
phy-names = "usb";
};
usb@2,0 {
reg = <0x11000 0 0 0 0>;
phys = <&usb2 0>;
phy-names = "usb";
};
};
usbphy: usb-phy@e6590100 {
compatible = "renesas,usb-phy-r8a7745",
"renesas,rcar-gen2-usb-phy";
reg = <0 0xe6590100 0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cpg CPG_MOD 704>;
clock-names = "usbhs";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 704>;
status = "disabled";
usb0: usb-channel@0 {
reg = <0>;
#phy-cells = <1>;
};
usb2: usb-channel@2 {
reg = <2>;
#phy-cells = <1>;
};
};
};
/* External root clock */

11
arch/arm/boot/dts/r8a7778.dtsi
View File

@ -33,6 +33,7 @@
compatible = "arm,cortex-a9";
reg = <0>;
clock-frequency = <800000000>;
clocks = <&z_clk>;
};
};
@ -88,7 +89,7 @@
};
gpio0: gpio@ffc40000 {
compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
reg = <0xffc40000 0x2c>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -99,7 +100,7 @@
};
gpio1: gpio@ffc41000 {
compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
reg = <0xffc41000 0x2c>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -110,7 +111,7 @@
};
gpio2: gpio@ffc42000 {
compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
reg = <0xffc42000 0x2c>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -121,7 +122,7 @@
};
gpio3: gpio@ffc43000 {
compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
reg = <0xffc43000 0x2c>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -132,7 +133,7 @@
};
gpio4: gpio@ffc44000 {
compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
reg = <0xffc44000 0x2c>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;

18
arch/arm/boot/dts/r8a7779.dtsi
View File

@ -29,12 +29,14 @@
compatible = "arm,cortex-a9";
reg = <0>;
clock-frequency = <1000000000>;
clocks = <&cpg_clocks R8A7779_CLK_Z>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
clock-frequency = <1000000000>;
clocks = <&cpg_clocks R8A7779_CLK_Z>;
power-domains = <&sysc R8A7779_PD_ARM1>;
};
cpu@2 {
@ -42,6 +44,7 @@
compatible = "arm,cortex-a9";
reg = <2>;
clock-frequency = <1000000000>;
clocks = <&cpg_clocks R8A7779_CLK_Z>;
power-domains = <&sysc R8A7779_PD_ARM2>;
};
cpu@3 {
@ -49,6 +52,7 @@
compatible = "arm,cortex-a9";
reg = <3>;
clock-frequency = <1000000000>;
clocks = <&cpg_clocks R8A7779_CLK_Z>;
power-domains = <&sysc R8A7779_PD_ARM3>;
};
};
@ -76,7 +80,7 @@
};
gpio0: gpio@ffc40000 {
compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
reg = <0xffc40000 0x2c>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -87,7 +91,7 @@
};
gpio1: gpio@ffc41000 {
compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
reg = <0xffc41000 0x2c>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -98,7 +102,7 @@
};
gpio2: gpio@ffc42000 {
compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
reg = <0xffc42000 0x2c>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -109,7 +113,7 @@
};
gpio3: gpio@ffc43000 {
compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
reg = <0xffc43000 0x2c>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -120,7 +124,7 @@
};
gpio4: gpio@ffc44000 {
compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
reg = <0xffc44000 0x2c>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -131,7 +135,7 @@
};
gpio5: gpio@ffc45000 {
compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
reg = <0xffc45000 0x2c>;
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -142,7 +146,7 @@
};
gpio6: gpio@ffc46000 {
compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
reg = <0xffc46000 0x2c>;
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;

35
arch/arm/boot/dts/r8a7790.dtsi
View File

@ -56,6 +56,7 @@
clock-latency = <300000>; /* 300 us */
power-domains = <&sysc R8A7790_PD_CA15_CPU0>;
next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>;
/* kHz - uV - OPPs unknown yet */
operating-points = <1400000 1000000>,
@ -71,8 +72,10 @@
compatible = "arm,cortex-a15";
reg = <1>;
clock-frequency = <1300000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
power-domains = <&sysc R8A7790_PD_CA15_CPU1>;
next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>;
};
cpu2: cpu@2 {
@ -80,8 +83,10 @@
compatible = "arm,cortex-a15";
reg = <2>;
clock-frequency = <1300000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
power-domains = <&sysc R8A7790_PD_CA15_CPU2>;
next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>;
};
cpu3: cpu@3 {
@ -89,8 +94,10 @@
compatible = "arm,cortex-a15";
reg = <3>;
clock-frequency = <1300000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
power-domains = <&sysc R8A7790_PD_CA15_CPU3>;
next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>;
};
cpu4: cpu@100 {
@ -98,8 +105,10 @@
compatible = "arm,cortex-a7";
reg = <0x100>;
clock-frequency = <780000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
power-domains = <&sysc R8A7790_PD_CA7_CPU0>;
next-level-cache = <&L2_CA7>;
capacity-dmips-mhz = <539>;
};
cpu5: cpu@101 {
@ -107,8 +116,10 @@
compatible = "arm,cortex-a7";
reg = <0x101>;
clock-frequency = <780000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
power-domains = <&sysc R8A7790_PD_CA7_CPU1>;
next-level-cache = <&L2_CA7>;
capacity-dmips-mhz = <539>;
};
cpu6: cpu@102 {
@ -116,8 +127,10 @@
compatible = "arm,cortex-a7";
reg = <0x102>;
clock-frequency = <780000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
power-domains = <&sysc R8A7790_PD_CA7_CPU2>;
next-level-cache = <&L2_CA7>;
capacity-dmips-mhz = <539>;
};
cpu7: cpu@103 {
@ -125,8 +138,10 @@
compatible = "arm,cortex-a7";
reg = <0x103>;
clock-frequency = <780000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
power-domains = <&sysc R8A7790_PD_CA7_CPU3>;
next-level-cache = <&L2_CA7>;
capacity-dmips-mhz = <539>;
};
L2_CA15: cache-controller-0 {
@ -192,7 +207,7 @@
};
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
reg = <0 0xe6050000 0 0x50>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -206,7 +221,7 @@
};
gpio1: gpio@e6051000 {
compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
reg = <0 0xe6051000 0 0x50>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -220,7 +235,7 @@
};
gpio2: gpio@e6052000 {
compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
reg = <0 0xe6052000 0 0x50>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -234,7 +249,7 @@
};
gpio3: gpio@e6053000 {
compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
reg = <0 0xe6053000 0 0x50>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -248,7 +263,7 @@
};
gpio4: gpio@e6054000 {
compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
reg = <0 0xe6054000 0 0x50>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -262,7 +277,7 @@
};
gpio5: gpio@e6055000 {
compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
reg = <0 0xe6055000 0 0x50>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -1014,7 +1029,7 @@
status = "disabled";
};
vsp1@fe920000 {
vsp@fe920000 {
compatible = "renesas,vsp1";
reg = <0 0xfe920000 0 0x8000>;
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
@ -1023,7 +1038,7 @@
resets = <&cpg 130>;
};
vsp1@fe928000 {
vsp@fe928000 {
compatible = "renesas,vsp1";
reg = <0 0xfe928000 0 0x8000>;
interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
@ -1032,7 +1047,7 @@
resets = <&cpg 131>;
};
vsp1@fe930000 {
vsp@fe930000 {
compatible = "renesas,vsp1";
reg = <0 0xfe930000 0 0x8000>;
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
@ -1041,7 +1056,7 @@
resets = <&cpg 128>;
};
vsp1@fe938000 {
vsp@fe938000 {
compatible = "renesas,vsp1";
reg = <0 0xfe938000 0 0x8000>;
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;

23
arch/arm/boot/dts/r8a7791.dtsi
View File

@ -70,6 +70,7 @@
compatible = "arm,cortex-a15";
reg = <1>;
clock-frequency = <1500000000>;
clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
power-domains = <&sysc R8A7791_PD_CA15_CPU1>;
next-level-cache = <&L2_CA15>;
};
@ -124,7 +125,7 @@
};
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
reg = <0 0xe6050000 0 0x50>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -138,7 +139,7 @@
};
gpio1: gpio@e6051000 {
compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
reg = <0 0xe6051000 0 0x50>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -152,7 +153,7 @@
};
gpio2: gpio@e6052000 {
compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
reg = <0 0xe6052000 0 0x50>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -166,7 +167,7 @@
};
gpio3: gpio@e6053000 {
compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
reg = <0 0xe6053000 0 0x50>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -180,7 +181,7 @@
};
gpio4: gpio@e6054000 {
compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
reg = <0 0xe6054000 0 0x50>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -194,7 +195,7 @@
};
gpio5: gpio@e6055000 {
compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
reg = <0 0xe6055000 0 0x50>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -208,7 +209,7 @@
};
gpio6: gpio@e6055400 {
compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
reg = <0 0xe6055400 0 0x50>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -222,7 +223,7 @@
};
gpio7: gpio@e6055800 {
compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
reg = <0 0xe6055800 0 0x50>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -1073,7 +1074,7 @@
status = "disabled";
};
vsp1@fe928000 {
vsp@fe928000 {
compatible = "renesas,vsp1";
reg = <0 0xfe928000 0 0x8000>;
interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
@ -1082,7 +1083,7 @@
resets = <&cpg 131>;
};
vsp1@fe930000 {
vsp@fe930000 {
compatible = "renesas,vsp1";
reg = <0 0xfe930000 0 0x8000>;
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
@ -1091,7 +1092,7 @@
resets = <&cpg 128>;
};
vsp1@fe938000 {
vsp@fe938000 {
compatible = "renesas,vsp1";
reg = <0 0xfe938000 0 0x8000>;
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;

31
arch/arm/boot/dts/r8a7792.dtsi
View File

@ -56,6 +56,7 @@
compatible = "arm,cortex-a15";
reg = <1>;
clock-frequency = <1000000000>;
clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
next-level-cache = <&L2_CA15>;
};
@ -147,7 +148,7 @@
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a7792",
"renesas,gpio-rcar";
"renesas,rcar-gen2-gpio";
reg = <0 0xe6050000 0 0x50>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -162,7 +163,7 @@
gpio1: gpio@e6051000 {
compatible = "renesas,gpio-r8a7792",
"renesas,gpio-rcar";
"renesas,rcar-gen2-gpio";
reg = <0 0xe6051000 0 0x50>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -177,7 +178,7 @@
gpio2: gpio@e6052000 {
compatible = "renesas,gpio-r8a7792",
"renesas,gpio-rcar";
"renesas,rcar-gen2-gpio";
reg = <0 0xe6052000 0 0x50>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -192,7 +193,7 @@
gpio3: gpio@e6053000 {
compatible = "renesas,gpio-r8a7792",
"renesas,gpio-rcar";
"renesas,rcar-gen2-gpio";
reg = <0 0xe6053000 0 0x50>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -207,7 +208,7 @@
gpio4: gpio@e6054000 {
compatible = "renesas,gpio-r8a7792",
"renesas,gpio-rcar";
"renesas,rcar-gen2-gpio";
reg = <0 0xe6054000 0 0x50>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -222,7 +223,7 @@
gpio5: gpio@e6055000 {
compatible = "renesas,gpio-r8a7792",
"renesas,gpio-rcar";
"renesas,rcar-gen2-gpio";
reg = <0 0xe6055000 0 0x50>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -237,7 +238,7 @@
gpio6: gpio@e6055100 {
compatible = "renesas,gpio-r8a7792",
"renesas,gpio-rcar";
"renesas,rcar-gen2-gpio";
reg = <0 0xe6055100 0 0x50>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -252,7 +253,7 @@
gpio7: gpio@e6055200 {
compatible = "renesas,gpio-r8a7792",
"renesas,gpio-rcar";
"renesas,rcar-gen2-gpio";
reg = <0 0xe6055200 0 0x50>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -267,7 +268,7 @@
gpio8: gpio@e6055300 {
compatible = "renesas,gpio-r8a7792",
"renesas,gpio-rcar";
"renesas,rcar-gen2-gpio";
reg = <0 0xe6055300 0 0x50>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -282,7 +283,7 @@
gpio9: gpio@e6055400 {
compatible = "renesas,gpio-r8a7792",
"renesas,gpio-rcar";
"renesas,rcar-gen2-gpio";
reg = <0 0xe6055400 0 0x50>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -297,7 +298,7 @@
gpio10: gpio@e6055500 {
compatible = "renesas,gpio-r8a7792",
"renesas,gpio-rcar";
"renesas,rcar-gen2-gpio";
reg = <0 0xe6055500 0 0x50>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -312,7 +313,7 @@
gpio11: gpio@e6055600 {
compatible = "renesas,gpio-r8a7792",
"renesas,gpio-rcar";
"renesas,rcar-gen2-gpio";
reg = <0 0xe6055600 0 0x50>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -794,7 +795,7 @@
status = "disabled";
};
vsp1@fe928000 {
vsp@fe928000 {
compatible = "renesas,vsp1";
reg = <0 0xfe928000 0 0x8000>;
interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
@ -803,7 +804,7 @@
resets = <&cpg 131>;
};
vsp1@fe930000 {
vsp@fe930000 {
compatible = "renesas,vsp1";
reg = <0 0xfe930000 0 0x8000>;
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
@ -812,7 +813,7 @@
resets = <&cpg 128>;
};
vsp1@fe938000 {
vsp@fe938000 {
compatible = "renesas,vsp1";
reg = <0 0xfe938000 0 0x8000>;
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;

17
arch/arm/boot/dts/r8a7793.dtsi
View File

@ -62,6 +62,7 @@
compatible = "arm,cortex-a15";
reg = <1>;
clock-frequency = <1500000000>;
clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
power-domains = <&sysc R8A7793_PD_CA15_CPU1>;
};
@ -115,7 +116,7 @@
};
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
reg = <0 0xe6050000 0 0x50>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -129,7 +130,7 @@
};
gpio1: gpio@e6051000 {
compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
reg = <0 0xe6051000 0 0x50>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -143,7 +144,7 @@
};
gpio2: gpio@e6052000 {
compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
reg = <0 0xe6052000 0 0x50>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -157,7 +158,7 @@
};
gpio3: gpio@e6053000 {
compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
reg = <0 0xe6053000 0 0x50>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -171,7 +172,7 @@
};
gpio4: gpio@e6054000 {
compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
reg = <0 0xe6054000 0 0x50>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -185,7 +186,7 @@
};
gpio5: gpio@e6055000 {
compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
reg = <0 0xe6055000 0 0x50>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -199,7 +200,7 @@
};
gpio6: gpio@e6055400 {
compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
reg = <0 0xe6055400 0 0x50>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -213,7 +214,7 @@
};
gpio7: gpio@e6055800 {
compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
reg = <0 0xe6055800 0 0x50>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;

19
arch/arm/boot/dts/r8a7794.dtsi
View File

@ -53,6 +53,7 @@
compatible = "arm,cortex-a7";
reg = <1>;
clock-frequency = <1000000000>;
clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
power-domains = <&sysc R8A7794_PD_CA7_CPU1>;
next-level-cache = <&L2_CA7>;
};
@ -82,7 +83,7 @@
};
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
reg = <0 0xe6050000 0 0x50>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -96,7 +97,7 @@
};
gpio1: gpio@e6051000 {
compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
reg = <0 0xe6051000 0 0x50>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -110,7 +111,7 @@
};
gpio2: gpio@e6052000 {
compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
reg = <0 0xe6052000 0 0x50>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -124,7 +125,7 @@
};
gpio3: gpio@e6053000 {
compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
reg = <0 0xe6053000 0 0x50>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -138,7 +139,7 @@
};
gpio4: gpio@e6054000 {
compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
reg = <0 0xe6054000 0 0x50>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -152,7 +153,7 @@
};
gpio5: gpio@e6055000 {
compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
reg = <0 0xe6055000 0 0x50>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -166,7 +167,7 @@
};
gpio6: gpio@e6055400 {
compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
reg = <0 0xe6055400 0 0x50>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -970,7 +971,7 @@
};
};
vsp1@fe928000 {
vsp@fe928000 {
compatible = "renesas,vsp1";
reg = <0 0xfe928000 0 0x8000>;
interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
@ -979,7 +980,7 @@
resets = <&cpg 131>;
};
vsp1@fe930000 {
vsp@fe930000 {
compatible = "renesas,vsp1";
reg = <0 0xfe930000 0 0x8000>;
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;

2
arch/arm/boot/dts/sh73a0.dtsi
View File

@ -27,6 +27,7 @@
compatible = "arm,cortex-a9";
reg = <0>;
clock-frequency = <1196000000>;
clocks = <&cpg_clocks SH73A0_CLK_Z>;
power-domains = <&pd_a2sl>;
next-level-cache = <&L2>;
};
@ -35,6 +36,7 @@
compatible = "arm,cortex-a9";
reg = <1>;
clock-frequency = <1196000000>;
clocks = <&cpg_clocks SH73A0_CLK_Z>;
power-domains = <&pd_a2sl>;
next-level-cache = <&L2>;
};

2
include/dt-bindings/clock/r7s72100-clock.h
View File

@ -11,6 +11,8 @@
#define __DT_BINDINGS_CLOCK_R7S72100_H__
#define R7S72100_CLK_PLL 0
#define R7S72100_CLK_I 1
#define R7S72100_CLK_G 2
/* MSTP2 */
#define R7S72100_CLK_CORESIGHT 0