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ASoC: amd: acp: Add ACP init()/deinit() callback for Renoir.
ACP hardware has PGFSM control registers that can be configured to power On/Off the ACP IP block. Add acp init()/de_init() callbacks in renoir platform driver probe()/remove() respectively to power on and off ACP IP block on ACP3X device. Signed-off-by: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> Link: https://lore.kernel.org/r/20220117115854.455995-5-AjitKumar.Pandey@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -25,6 +25,20 @@
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#define DRV_NAME "acp_asoc_renoir"
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#define ACP_SOFT_RST_DONE_MASK 0x00010001
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#define ACP_PWR_ON_MASK 0x01
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#define ACP_PWR_OFF_MASK 0x00
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#define ACP_PGFSM_STAT_MASK 0x03
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#define ACP_POWERED_ON 0x00
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#define ACP_PWR_ON_IN_PROGRESS 0x01
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#define ACP_POWERED_OFF 0x02
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#define DELAY_US 5
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#define ACP_TIMEOUT 500
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#define ACP_ERROR_MASK 0x20000000
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#define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF
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static struct snd_soc_acpi_codecs amp_rt1019 = {
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.num_codecs = 1,
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.codecs = {"10EC1019"}
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@ -112,11 +126,130 @@ static struct snd_soc_dai_driver acp_renoir_dai[] = {
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},
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};
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static int acp3x_power_on(void __iomem *base)
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{
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u32 val;
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val = readl(base + ACP_PGFSM_STATUS);
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if (val == ACP_POWERED_ON)
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return 0;
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if ((val & ACP_PGFSM_STAT_MASK) != ACP_PWR_ON_IN_PROGRESS)
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writel(ACP_PWR_ON_MASK, base + ACP_PGFSM_CONTROL);
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return readl_poll_timeout(base + ACP_PGFSM_STATUS, val, !val, DELAY_US, ACP_TIMEOUT);
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}
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static int acp3x_power_off(void __iomem *base)
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{
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u32 val;
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writel(ACP_PWR_OFF_MASK, base + ACP_PGFSM_CONTROL);
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return readl_poll_timeout(base + ACP_PGFSM_STATUS, val,
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(val & ACP_PGFSM_STAT_MASK) == ACP_POWERED_OFF,
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DELAY_US, ACP_TIMEOUT);
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}
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static int acp3x_reset(void __iomem *base)
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{
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u32 val;
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int ret;
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writel(1, base + ACP_SOFT_RESET);
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ret = readl_poll_timeout(base + ACP_SOFT_RESET, val, val & ACP_SOFT_RST_DONE_MASK,
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DELAY_US, ACP_TIMEOUT);
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if (ret)
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return ret;
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writel(0, base + ACP_SOFT_RESET);
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return readl_poll_timeout(base + ACP_SOFT_RESET, val, !val, DELAY_US, ACP_TIMEOUT);
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}
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static void acp3x_enable_interrupts(void __iomem *base)
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{
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u32 ext_intr_ctrl;
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writel(0x01, base + ACP_EXTERNAL_INTR_ENB);
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ext_intr_ctrl = readl(base + ACP_EXTERNAL_INTR_CNTL);
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ext_intr_ctrl |= ACP_ERROR_MASK;
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writel(ext_intr_ctrl, base + ACP_EXTERNAL_INTR_CNTL);
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}
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static void acp3x_disable_interrupts(void __iomem *base)
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{
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writel(ACP_EXT_INTR_STAT_CLEAR_MASK, base + ACP_EXTERNAL_INTR_STAT);
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writel(0x00, base + ACP_EXTERNAL_INTR_ENB);
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}
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static int rn_acp_init(void __iomem *base)
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{
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int ret;
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/* power on */
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ret = acp3x_power_on(base);
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if (ret)
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return ret;
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writel(0x01, base + ACP_CONTROL);
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/* Reset */
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ret = acp3x_reset(base);
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if (ret)
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return ret;
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acp3x_enable_interrupts(base);
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return 0;
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}
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static int rn_acp_deinit(void __iomem *base)
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{
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int ret = 0;
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acp3x_disable_interrupts(base);
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/* Reset */
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ret = acp3x_reset(base);
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if (ret)
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return ret;
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writel(0x00, base + ACP_CONTROL);
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/* power off */
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ret = acp3x_power_off(base);
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if (ret)
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return ret;
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return 0;
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}
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static int renoir_audio_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct acp_chip_info *chip;
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struct acp_dev_data *adata;
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struct resource *res;
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int ret;
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chip = dev_get_platdata(&pdev->dev);
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if (!chip || !chip->base) {
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dev_err(&pdev->dev, "ACP chip data is NULL\n");
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return -ENODEV;
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}
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if (chip->acp_rev != ACP3X_DEV) {
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dev_err(&pdev->dev, "Un-supported ACP Revision %d\n", chip->acp_rev);
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return -ENODEV;
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}
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ret = rn_acp_init(chip->base);
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if (ret) {
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dev_err(&pdev->dev, "ACP Init failed\n");
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return -EINVAL;
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}
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adata = devm_kzalloc(dev, sizeof(struct acp_dev_data), GFP_KERNEL);
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if (!adata)
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@ -155,6 +288,20 @@ static int renoir_audio_probe(struct platform_device *pdev)
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static int renoir_audio_remove(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct acp_chip_info *chip;
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int ret;
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chip = dev_get_platdata(&pdev->dev);
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if (!chip || !chip->base) {
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dev_err(&pdev->dev, "ACP chip data is NULL\n");
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return -ENODEV;
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}
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ret = rn_acp_deinit(chip->base);
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if (ret) {
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dev_err(&pdev->dev, "ACP de-init Failed\n");
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return -EINVAL;
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}
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acp_platform_unregister(dev);
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return 0;
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@ -14,6 +14,12 @@
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#define ACPAXI2AXI_ATU_CTRL 0xC40
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#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0xC20
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#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0xC24
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#define ACP_PGFSM_CONTROL 0x141C
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#define ACP_PGFSM_STATUS 0x1420
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#define ACP_SOFT_RESET 0x1000
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#define ACP_CONTROL 0x1004
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#define ACP_EXTERNAL_INTR_ENB 0x1800
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#define ACP_EXTERNAL_INTR_CNTL 0x1804
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#define ACP_EXTERNAL_INTR_STAT 0x1808
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